ARM: omap: clean redundant PISMO_xx macros used in OMAP3

[oweals/u-boot.git] / arch / arm / include / asm / arch-omap5 / clock.h

diff --git a/arch/arm/include/asm/arch-omap5/clock.h b/arch/arm/include/asm/arch-omap5/clock.h
index 3adfc090fe963bef1549fc0f3f54ee5a1b09c187..30d9de276492caf863b3d93429cb099bfdb9e0e4 100644 (file)
--- a/arch/arm/include/asm/arch-omap5/clock.h
+++ b/arch/arm/include/asm/arch-omap5/clock.h
@@ -137,6 +137,9 @@
 #define HSMMC_CLKCTRL_CLKSEL_MASK              (1 << 24)
 #define HSMMC_CLKCTRL_CLKSEL_DIV_MASK          (1 << 25)
 
+/* CM_L3INIT_SATA_CLKCTRL */
+#define SATA_CLKCTRL_OPTFCLKEN_MASK            (1 << 8)
+
 /* CM_WKUP_GPTIMER1_CLKCTRL */
 #define GPTIMER1_CLKCTRL_CLKSEL_MASK           (1 << 24)
 
@@ -149,6 +152,33 @@
 /* CM_L3INIT_USBPHY_CLKCTRL */
 #define USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK  8
 
+/* CM_L3INIT_USB_HOST_HS_CLKCTRL */
+#define OPTFCLKEN_FUNC48M_CLK                  (1 << 15)
+#define OPTFCLKEN_HSIC480M_P2_CLK              (1 << 14)
+#define OPTFCLKEN_HSIC480M_P1_CLK              (1 << 13)
+#define OPTFCLKEN_HSIC60M_P2_CLK               (1 << 12)
+#define OPTFCLKEN_HSIC60M_P1_CLK               (1 << 11)
+#define OPTFCLKEN_UTMI_P3_CLK                  (1 << 10)
+#define OPTFCLKEN_UTMI_P2_CLK                  (1 << 9)
+#define OPTFCLKEN_UTMI_P1_CLK                  (1 << 8)
+#define OPTFCLKEN_HSIC480M_P3_CLK              (1 << 7)
+#define OPTFCLKEN_HSIC60M_P3_CLK               (1 << 6)
+
+/* CM_L3INIT_USB_TLL_HS_CLKCTRL */
+#define OPTFCLKEN_USB_CH0_CLK_ENABLE   (1 << 8)
+#define OPTFCLKEN_USB_CH1_CLK_ENABLE   (1 << 9)
+#define OPTFCLKEN_USB_CH2_CLK_ENABLE   (1 << 10)
+
+/* CM_COREAON_USB_PHY_CORE_CLKCTRL */
+#define USBPHY_CORE_CLKCTRL_OPTFCLKEN_CLK32K   (1 << 8)
+
+/* CM_L3INIT_USB_OTG_SS_CLKCTRL */
+#define OTG_SS_CLKCTRL_MODULEMODE_HW   (1 << 0)
+#define OPTFCLKEN_REFCLK960M                   (1 << 8)
+
+/* CM_L3INIT_OCP2SCP1_CLKCTRL */
+#define OCP2SCP1_CLKCTRL_MODULEMODE_HW (1 << 0)
+
 /* CM_MPU_MPU_CLKCTRL */
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_SHIFT 24
 #define MPU_CLKCTRL_CLKSEL_EMIF_DIV_MODE_MASK  (3 << 24)
@@ -175,6 +205,10 @@
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ    400
 
+/* CTRL_CORE_SRCOMP_NORTH_SIDE */
+#define USB2PHY_DISCHGDET      (1 << 29)
+#define USB2PHY_AUTORESUME_EN (1 << 30)
+
 /* SMPS */
 #define SMPS_I2C_SLAVE_ADDR    0x12
 #define SMPS_REG_ADDR_12_MPU   0x23
@@ -288,6 +322,9 @@
 
 #define V_SCLK V_OSCK
 
+/* CKO buffer control */
+#define CKOBUFFER_CLK_ENABLE_MASK      (1 << 28)
+
 /* AUXCLKx reg fields */
 #define AUXCLK_ENABLE_MASK             (1 << 8)
 #define AUXCLK_SRCSELECT_SHIFT         1