Merge branch 'master' of git://git.denx.de/u-boot-arm

[oweals/u-boot.git] / arch / arm / include / asm / arch-omap4 / omap.h

diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 4d8c89ffbdff1450cc882d54f4840319aa91817a..d4b5076108603151328956df936e47f6b971a904 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -101,29 +101,18 @@
 #define TCLR_AR                        (0x1 << 1)
 #define TCLR_PRE               (0x1 << 5)
 
-/*
- * PRCM
- */
-
-/* PRM */
-#define PRM_BASE               0x4A306000
-#define PRM_DEVICE_BASE                (PRM_BASE + 0x1B00)
-
-#define PRM_RSTCTRL            PRM_DEVICE_BASE
-#define PRM_RSTCTRL_RESET      0x01
-
 /* Control Module */
 #define LDOSRAM_ACTMODE_VSET_IN_MASK   (0x1F << 5)
 #define LDOSRAM_VOLT_CTRL_OVERRIDE     0x0401040f
 #define CONTROL_EFUSE_1_OVERRIDE       0x1C4D0110
-#define CONTROL_EFUSE_2_OVERRIDE       0x00084000
+#define CONTROL_EFUSE_2_OVERRIDE       0x99084000
 
 /* LPDDR2 IO regs */
 #define CONTROL_LPDDR2IO_SLEW_125PS_DRV8_PULL_DOWN     0x1C1C1C1C
 #define CONTROL_LPDDR2IO_SLEW_325PS_DRV8_GATE_KEEPER   0x9E9E9E9E
 #define CONTROL_LPDDR2IO_SLEW_315PS_DRV12_PULL_DOWN    0x7C7C7C7C
 #define LPDDR2IO_GR10_WD_MASK                          (3 << 17)
-#define CONTROL_LPDDR2IO_3_VAL         0xA0888C00
+#define CONTROL_LPDDR2IO_3_VAL         0xA0888C0F
 
 /* CONTROL_EFUSE_2 */
 #define CONTROL_EFUSE_2_NMOS_PMOS_PTV_CODE_1           0x00ffc000
@@ -139,18 +128,24 @@ struct s32ktimer {
        unsigned int s32k_cr;   /* 0x10 */
 };
 
-struct omap4_sys_ctrl_regs {
+#define DEVICE_TYPE_SHIFT (0x8)
+#define DEVICE_TYPE_MASK (0x7 << DEVICE_TYPE_SHIFT)
+#define DEVICE_GP 0x3
+
+struct omap_sys_ctrl_regs {
        unsigned int pad1[129];
        unsigned int control_id_code;                   /* 0x4A002204 */
        unsigned int pad11[22];
        unsigned int control_std_fuse_opp_bgap;         /* 0x4a002260 */
-       unsigned int pad2[47];
+       unsigned int pad2[24];                          /* 0x4a002264 */
+       unsigned int control_status;                    /* 0x4a0022c4 */
+       unsigned int pad3[22];                          /* 0x4a0022c8 */
        unsigned int control_ldosram_iva_voltage_ctrl;  /* 0x4A002320 */
        unsigned int control_ldosram_mpu_voltage_ctrl;  /* 0x4A002324 */
        unsigned int control_ldosram_core_voltage_ctrl; /* 0x4A002328 */
-       unsigned int pad3[260277];
+       unsigned int pad4[260277];
        unsigned int control_pbiaslite;                 /* 0x4A100600 */
-       unsigned int pad4[63];
+       unsigned int pad5[63];
        unsigned int control_efuse_1;                   /* 0x4A100700 */
        unsigned int control_efuse_2;                   /* 0x4A100704 */
 };
@@ -177,7 +172,6 @@ struct control_lpddr2io_regs {
 /* base address for indirect vectors (internal boot mode) */
 #define SRAM_ROM_VECT_BASE     0x4030D000
 /* Temporary SRAM stack used while low level init is done */
-#define LOW_LEVEL_SRAM_STACK           NON_SECURE_SRAM_END
 #define SRAM_SCRATCH_SPACE_ADDR                NON_SECURE_SRAM_START
 /* SRAM scratch space entries */
 #define OMAP4_SRAM_SCRATCH_OMAP4_REV   SRAM_SCRATCH_SPACE_ADDR