tegra124: clock: Add display clocks and functions

[oweals/u-boot.git] / arch / arm / include / asm / arch-omap4 / clock.h

diff --git a/arch/arm/include/asm/arch-omap4/clock.h b/arch/arm/include/asm/arch-omap4/clock.h
index f544edfbd0afa3e3ace5055a8a1f744ece35d330..f3a682a19715675b0c5ad9ef202df7145d7dcc3c 100644 (file)
--- a/arch/arm/include/asm/arch-omap4/clock.h
+++ b/arch/arm/include/asm/arch-omap4/clock.h
@@ -4,23 +4,7 @@
  *
  * Aneesh V <aneesh@ti.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _CLOCKS_OMAP4_H_
 #define _CLOCKS_OMAP4_H_
@@ -76,7 +60,7 @@
 #define CM_CLKSEL_DCC_EN_MASK                  (1 << 22)
 
 /* CM_SYS_CLKSEL */
-#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
+#define CM_SYS_CLKSEL_SYS_CLKSEL_MASK  7
 
 /* CM_CLKSEL_CORE */
 #define CLKSEL_CORE_SHIFT      0
@@ -165,11 +149,16 @@
 /* PRM_VC_VAL_BYPASS */
 #define PRM_VC_I2C_CHANNEL_FREQ_KHZ    400
 
-/* SMPS */
+/* PMIC */
 #define SMPS_I2C_SLAVE_ADDR    0x12
+/* TWL6030 SMPS */
 #define SMPS_REG_ADDR_VCORE1   0x55
 #define SMPS_REG_ADDR_VCORE2   0x5B
 #define SMPS_REG_ADDR_VCORE3   0x61
+/* TWL6032 SMPS */
+#define SMPS_REG_ADDR_SMPS1    0x55
+#define SMPS_REG_ADDR_SMPS2    0x5B
+#define SMPS_REG_ADDR_SMPS5    0x49
 
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV             607700
 #define PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV 709000
@@ -214,6 +203,10 @@
 #define DPLL_NO_LOCK   0
 #define DPLL_LOCK      1
 
+/* Clock Defines */
+#define V_OSCK                 38400000        /* Clock output from T2 */
+#define V_SCLK                   V_OSCK
+
 struct omap4_scrm_regs {
        u32 revision;           /* 0x0000 */
        u32 pad00[63];