arm: rmobile: alt: Update to QoS revision 0.31 and 0.321

[oweals/u-boot.git] / arch / arm / include / asm / arch-omap3 / dss.h

diff --git a/arch/arm/include/asm/arch-omap3/dss.h b/arch/arm/include/asm/arch-omap3/dss.h
index 4c56e5e9e677daaa57f809f144688d09ec7b04e1..8bf6b4895fcbcef56a23d307e7f08912a226a810 100644 (file)
--- a/arch/arm/include/asm/arch-omap3/dss.h
+++ b/arch/arm/include/asm/arch-omap3/dss.h
@@ -28,15 +28,19 @@
 #ifndef DSS_H
 #define DSS_H
 
-/*
- * DSS Base Registers
- */
-#define OMAP3_DSS_BASE         0x48050040
-#define OMAP3_DISPC_BASE       0x48050440
+/* DSS Base Registers */
+#define OMAP3_DSS_BASE         0x48050000
+#define OMAP3_DISPC_BASE       0x48050400
 #define OMAP3_VENC_BASE                0x48050C00
 
 /* DSS Registers */
 struct dss_regs {
+       u32 revision;                           /* 0x00 */
+       u8 res1[12];                            /* 0x04 */
+       u32 sysconfig;                          /* 0x10 */
+       u32 sysstatus;                          /* 0x14 */
+       u32 irqstatus;                          /* 0x18 */
+       u8 res2[36];                            /* 0x1C */
        u32 control;                            /* 0x40 */
        u32 sdi_control;                        /* 0x44 */
        u32 pll_control;                        /* 0x48 */
@@ -44,6 +48,13 @@ struct dss_regs {
 
 /* DISPC Registers */
 struct dispc_regs {
+       u32 revision;                           /* 0x00 */
+       u8 res1[12];                            /* 0x04 */
+       u32 sysconfig;                          /* 0x10 */
+       u32 sysstatus;                          /* 0x14 */
+       u32 irqstatus;                          /* 0x18 */
+       u32 irqenable;                          /* 0x1C */
+       u8 res2[32];                            /* 0x20 */
        u32 control;                            /* 0x40 */
        u32 config;                             /* 0x44 */
        u32 reserve_2;                          /* 0x48 */
@@ -60,6 +71,18 @@ struct dispc_regs {
        u32 global_alpha;                       /* 0x74 */
        u32 size_dig;                           /* 0x78 */
        u32 size_lcd;                           /* 0x7C */
+       u32 gfx_ba0;                            /* 0x80 */
+       u32 gfx_ba1;                            /* 0x84 */
+       u32 gfx_position;                       /* 0x88 */
+       u32 gfx_size;                           /* 0x8C */
+       u8 unused[16];                          /* 0x90 */
+       u32 gfx_attributes;                     /* 0xA0 */
+       u32 gfx_fifo_threshold;                 /* 0xA4 */
+       u32 gfx_fifo_size_status;               /* 0xA8 */
+       u32 gfx_row_inc;                        /* 0xAC */
+       u32 gfx_pixel_inc;                      /* 0xB0 */
+       u32 gfx_window_skip;                    /* 0xB4 */
+       u32 gfx_table_ba;                       /* 0xB8 */
 };
 
 /* VENC Registers */
@@ -119,10 +142,16 @@ struct venc_regs {
 };
 
 /* Few Register Offsets */
-#define FRAME_MODE_SHIFT                       1
 #define TFTSTN_SHIFT                           3
 #define DATALINES_SHIFT                                8
 
+#define GFX_ENABLE                             1
+#define GFX_FORMAT_SHIFT                       1
+#define LOADMODE_SHIFT                         1
+
+#define DSS_SOFTRESET                          (1 << 1)
+#define DSS_RESETDONE                          1
+
 /* Enabling Display controller */
 #define LCD_ENABLE                             1
 #define DIG_ENABLE                             (1 << 1)
@@ -131,26 +160,45 @@ struct venc_regs {
 #define GP_OUT0                                        (1 << 15)
 #define GP_OUT1                                        (1 << 16)
 
-#define DISPC_ENABLE                           (LCD_ENABLE | \
-                                                DIG_ENABLE | \
-                                                GO_LCD | \
-                                                GO_DIG | \
-                                                GP_OUT0| \
-                                                GP_OUT1)
-
 /* Configure VENC DSS Params */
 #define VENC_CLK_ENABLE                                (1 << 3)
 #define DAC_DEMEN                              (1 << 4)
 #define DAC_POWERDN                            (1 << 5)
 #define VENC_OUT_SEL                           (1 << 6)
 #define DIG_LPP_SHIFT                          16
-#define VENC_DSS_CONFIG                                (VENC_CLK_ENABLE | \
-                                                DAC_DEMEN | \
-                                                DAC_POWERDN | \
-                                                VENC_OUT_SEL)
-/*
- * Panel Configuration
- */
+
+/* LCD display type */
+#define PASSIVE_DISPLAY                        0
+#define ACTIVE_DISPLAY                 1
+
+/* TFTDATALINES */
+#define LCD_INTERFACE_12_BIT   0
+#define LCD_INTERFACE_16_BIT   1
+#define LCD_INTERFACE_18_BIT   2
+#define LCD_INTERFACE_24_BIT   3
+
+/* Polarity */
+#define DSS_IVS                (1 << 12)
+#define DSS_IHS                (1 << 13)
+#define DSS_IPC                (1 << 14)
+#define DSS_IEO                (1 << 15)
+#define DSS_ONOFF      (1 << 17)
+
+/* GFX format */
+#define GFXFORMAT_BITMAP1              (0x0 << 1)
+#define GFXFORMAT_BITMAP2              (0x1 << 1)
+#define GFXFORMAT_BITMAP4              (0x2 << 1)
+#define GFXFORMAT_BITMAP8              (0x3 << 1)
+#define GFXFORMAT_RGB12                        (0x4 << 1)
+#define GFXFORMAT_ARGB16               (0x5 << 1)
+#define GFXFORMAT_RGB16                        (0x6 << 1)
+#define GFXFORMAT_RGB24_UNPACKED       (0x8 << 1)
+#define GFXFORMAT_RGB24_PACKED         (0x9 << 1)
+#define GFXFORMAT_ARGB32               (0xC << 1)
+#define GFXFORMAT_RGBA32               (0xD << 1)
+#define GFXFORMAT_RGBx32               (0xE << 1)
+
+/* Panel Configuration */
 struct panel_config {
        u32 timing_h;
        u32 timing_v;
@@ -161,11 +209,22 @@ struct panel_config {
        u32 data_lines;
        u32 load_mode;
        u32 panel_color;
+       u32 gfx_format;
+       void *frame_buffer;
 };
 
-/*
- * Generic DSS Functions
- */
+#define DSS_HBP(bp)    (((bp) - 1) << 20)
+#define DSS_HFP(fp)    (((fp) - 1) << 8)
+#define DSS_HSW(sw)    ((sw) - 1)
+#define DSS_VBP(bp)    ((bp) << 20)
+#define DSS_VFP(fp)    ((fp) << 8)
+#define DSS_VSW(sw)    ((sw) - 1)
+
+#define PANEL_TIMING_H(bp, fp, sw) (DSS_HBP(bp) | DSS_HFP(fp) | DSS_HSW(sw))
+#define PANEL_TIMING_V(bp, fp, sw) (DSS_VBP(bp) | DSS_VFP(fp) | DSS_VSW(sw))
+#define PANEL_LCD_SIZE(xres, yres) ((yres - 1) << 16 | (xres - 1))
+
+/* Generic DSS Functions */
 void omap3_dss_venc_config(const struct venc_regs *venc_cfg,
                        u32 height, u32 width);
 void omap3_dss_panel_config(const struct panel_config *panel_cfg);