Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx6 / mx6-ddr.h

diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index d544d2e7086009fc0d083816b6233610af556221..c49aa6290c6a6b0d28ddd70f0b0c5b90cd019353 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -13,7 +13,11 @@
 #if defined(CONFIG_MX6DL) || defined(CONFIG_MX6S)
 #include "mx6dl-ddr.h"
 #else
+#ifdef CONFIG_MX6SX
+#include "mx6sx-ddr.h"
+#else
 #error "Please select cpu"
+#endif /* CONFIG_MX6SX */
 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
 #endif /* CONFIG_MX6Q */
 #else
@@ -58,6 +62,49 @@ struct mmdc_p_regs {
        u32 mpmur0;
 };
 
+#define MX6SX_IOM_DDR_BASE     0x020e0200
+struct mx6sx_iomux_ddr_regs {
+       u32 res1[59];
+       u32 dram_dqm0;
+       u32 dram_dqm1;
+       u32 dram_dqm2;
+       u32 dram_dqm3;
+       u32 dram_ras;
+       u32 dram_cas;
+       u32 res2[2];
+       u32 dram_sdwe_b;
+       u32 dram_odt0;
+       u32 dram_odt1;
+       u32 dram_sdba0;
+       u32 dram_sdba1;
+       u32 dram_sdba2;
+       u32 dram_sdcke0;
+       u32 dram_sdcke1;
+       u32 dram_sdclk_0;
+       u32 dram_sdqs0;
+       u32 dram_sdqs1;
+       u32 dram_sdqs2;
+       u32 dram_sdqs3;
+       u32 dram_reset;
+};
+
+#define MX6SX_IOM_GRP_BASE     0x020e0500
+struct mx6sx_iomux_grp_regs {
+       u32 res1[61];
+       u32 grp_addds;
+       u32 grp_ddrmode_ctl;
+       u32 grp_ddrpke;
+       u32 grp_ddrpk;
+       u32 grp_ddrhys;
+       u32 grp_ddrmode;
+       u32 grp_b0ds;
+       u32 grp_b1ds;
+       u32 grp_ctlds;
+       u32 grp_ddr_type;
+       u32 grp_b2ds;
+       u32 grp_b3ds;
+};
+
 /*
  * MMDC iomux registers (pinctl/padctl) - (different for IMX6DQ vs IMX6SDL)
  */
@@ -203,6 +250,7 @@ struct mx6_ddr_sysinfo {
        u8 mif3_mode;   /* Command prediction working mode */
        u8 rst_to_cke;  /* Time from SDE enable to CKE rise */
        u8 sde_to_rst;  /* Time from SDE enable until DDR reset# is high */
+       u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
 };
 
 /*
@@ -239,6 +287,9 @@ void mx6dq_dram_iocfg(unsigned width,
 void mx6sdl_dram_iocfg(unsigned width,
                       const struct mx6sdl_iomux_ddr_regs *,
                       const struct mx6sdl_iomux_grp_regs *);
+void mx6sx_dram_iocfg(unsigned width,
+                     const struct mx6sx_iomux_ddr_regs *,
+                     const struct mx6sx_iomux_grp_regs *);
 
 /* configure mx6 mmdc registers */
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,