Merge branch 'master' of git://git.denx.de/u-boot-video

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx6 / mx6-ddr.h

diff --git a/arch/arm/include/asm/arch-mx6/mx6-ddr.h b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
index f3194dadb601ae34e907297fe81a3cc3f63de75d..68d9bda2c5ce984faade0094fcd8d8f1b88c5ae9 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/mx6-ddr.h
+++ b/arch/arm/include/asm/arch-mx6/mx6-ddr.h
@@ -19,13 +19,22 @@
 #ifdef CONFIG_MX6UL
 #include "mx6ul-ddr.h"
 #else
+#ifdef CONFIG_MX6SL
+#include "mx6sl-ddr.h"
+#else
 #error "Please select cpu"
+#endif /* CONFIG_MX6SL */
 #endif /* CONFIG_MX6UL */
 #endif /* CONFIG_MX6SX */
 #endif /* CONFIG_MX6DL or CONFIG_MX6S */
 #endif /* CONFIG_MX6Q */
 #else
 
+enum {
+       DDR_TYPE_DDR3,
+       DDR_TYPE_LPDDR2,
+};
+
 /* MMDC P0/P1 Registers */
 struct mmdc_p_regs {
        u32 mdctl;
@@ -113,6 +122,49 @@ struct mmdc_p_regs {
        u32 mpdccr;
 };
 
+#define MX6SL_IOM_DDR_BASE     0x020e0300
+struct mx6sl_iomux_ddr_regs {
+       u32 dram_cas;
+       u32 dram_cs0_b;
+       u32 dram_cs1_b;
+       u32 dram_dqm0;
+       u32 dram_dqm1;
+       u32 dram_dqm2;
+       u32 dram_dqm3;
+       u32 dram_ras;
+       u32 dram_reset;
+       u32 dram_sdba0;
+       u32 dram_sdba1;
+       u32 dram_sdba2;
+       u32 dram_sdcke0;
+       u32 dram_sdcke1;
+       u32 dram_sdclk_0;
+       u32 dram_odt0;
+       u32 dram_odt1;
+       u32 dram_sdqs0;
+       u32 dram_sdqs1;
+       u32 dram_sdqs2;
+       u32 dram_sdqs3;
+       u32 dram_sdwe_b;
+};
+
+#define MX6SL_IOM_GRP_BASE     0x020e0500
+struct mx6sl_iomux_grp_regs {
+       u32 res1[43];
+       u32 grp_addds;
+       u32 grp_ddrmode_ctl;
+       u32 grp_ddrpke;
+       u32 grp_ddrpk;
+       u32 grp_ddrhys;
+       u32 grp_ddrmode;
+       u32 grp_b0ds;
+       u32 grp_ctlds;
+       u32 grp_b1ds;
+       u32 grp_ddr_type;
+       u32 grp_b2ds;
+       u32 grp_b3ds;
+};
+
 #define MX6UL_IOM_DDR_BASE     0x020e0200
 struct mx6ul_iomux_ddr_regs {
        u32 res1[17];
@@ -325,6 +377,21 @@ struct mx6_ddr3_cfg {
        u8 SRT;         /* self-refresh temperature: 0=normal, 1=extended */
 };
 
+/* Device Information: Varies per LPDDR2 part number and speed grade */
+struct mx6_lpddr2_cfg {
+       u16 mem_speed;  /* ie 800 for LPDDR2-800 */
+       u8 density;     /* chip density (Gb) (1,2,4,8) */
+       u8 width;       /* bus width (bits) (4,8,16) */
+       u8 banks;       /* number of banks */
+       u8 rowaddr;     /* row address bits (11-16)*/
+       u8 coladdr;     /* col address bits (9-12) */
+       u16 trcd_lp;
+       u16 trppb_lp;
+       u16 trpab_lp;
+       u16 trcmin;     /* tRC min (ns*100) */
+       u16 trasmin;    /* tRAS min (ns*100) */
+};
+
 /* System Information: Varies per board design, layout, and term choices */
 struct mx6_ddr_sysinfo {
        u8 dsize;       /* size of bus (in dwords: 0=16bit,1=32bit,2=64bit) */
@@ -340,6 +407,7 @@ struct mx6_ddr_sysinfo {
        u8 rst_to_cke;  /* Time from SDE enable to CKE rise */
        u8 sde_to_rst;  /* Time from SDE enable until DDR reset# is high */
        u8 pd_fast_exit;/* enable precharge powerdown fast-exit */
+       u8 ddr_type;    /* DDR type: DDR3(0) or LPDDR2(1) */
 };
 
 /*
@@ -367,6 +435,8 @@ struct mx6_mmdc_calibration {
        /* write delay */
        u32 p0_mpwrdlctl;
        u32 p1_mpwrdlctl;
+       /* lpddr2 zq hw calibration */
+       u32 mpzqlp2ctl;
 };
 
 /* configure iomux (pinctl/padctl) */
@@ -382,11 +452,14 @@ void mx6sx_dram_iocfg(unsigned width,
 void mx6ul_dram_iocfg(unsigned width,
                      const struct mx6ul_iomux_ddr_regs *,
                      const struct mx6ul_iomux_grp_regs *);
+void mx6sl_dram_iocfg(unsigned width,
+                     const struct mx6sl_iomux_ddr_regs *,
+                     const struct mx6sl_iomux_grp_regs *);
 
 /* configure mx6 mmdc registers */
 void mx6_dram_cfg(const struct mx6_ddr_sysinfo *,
                  const struct mx6_mmdc_calibration *,
-                 const struct mx6_ddr3_cfg *);
+                 const void *);
 
 #endif /* CONFIG_SPL_BUILD */