Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-net

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx6 / iomux.h

diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h
index f4cfd4f92125b7d1b802a602a2570521eb73a35f..bea0bbb02b2303820ad3c70087e24ecf0215e05b 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/iomux.h
+++ b/arch/arm/include/asm/arch-mx6/iomux.h
@@ -1,6 +1,4 @@
-/*
- * SPDX-License-Identifier:    GPL-2.0+
- */
+/* SPDX-License-Identifier: GPL-2.0+ */
 
 #ifndef __ASM_ARCH_IOMUX_H__
 #define __ASM_ARCH_IOMUX_H__
@@ -9,6 +7,50 @@
 #define MX6_IOMUXC_GPR6                0x020e0018
 #define MX6_IOMUXC_GPR7                0x020e001c
 
+/*
+ * IOMUXC_GPR1 bit fields
+ */
+#define IOMUXC_GPR1_OTG_ID_ENET_RX_ERR (0<<13)
+#define IOMUXC_GPR1_OTG_ID_GPIO1       (1<<13)
+#define IOMUXC_GPR1_OTG_ID_MASK                (1<<13)
+#define IOMUXC_GPR1_REF_SSP_EN                 (1 << 16)
+#define IOMUXC_GPR1_TEST_POWERDOWN             (1 << 18)
+
+#define IOMUXC_GPR1_PCIE_SW_RST                (1 << 29)
+
+/*
+ * IOMUXC_GPR5 bit fields
+ */
+#define IOMUXC_GPR5_PCIE_BTNRST                        (1 << 19)
+#define IOMUXC_GPR5_PCIE_PERST                 (1 << 18)
+
+/*
+ * IOMUXC_GPR8 bit fields
+ */
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK            (0x3f << 0)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET          0
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_MASK      (0x3f << 6)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET    6
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_MASK                (0x3f << 12)
+#define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET      12
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_MASK             (0x7f << 18)
+#define IOMUXC_GPR8_PCS_TX_SWING_FULL_OFFSET           18
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_MASK              (0x7f << 25)
+#define IOMUXC_GPR8_PCS_TX_SWING_LOW_OFFSET            25
+
+/*
+ * IOMUXC_GPR12 bit fields
+ */
+#define IOMUXC_GPR12_RX_EQ_2                   (0x2 << 0)
+#define IOMUXC_GPR12_RX_EQ_MASK                        (0x7 << 0)
+#define IOMUXC_GPR12_LOS_LEVEL_9               (0x9 << 4)
+#define IOMUXC_GPR12_LOS_LEVEL_MASK            (0x1f << 4)
+#define IOMUXC_GPR12_APPS_LTSSM_ENABLE         (1 << 10)
+#define IOMUXC_GPR12_DEVICE_TYPE_EP            (0x0 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_RC            (0x4 << 12)
+#define IOMUXC_GPR12_DEVICE_TYPE_MASK          (0xf << 12)
+#define IOMUXC_GPR12_TEST_POWERDOWN            (1 << 30)
+
 /*
  * IOMUXC_GPR13 bit fields
  */
@@ -27,6 +69,21 @@
 #define IOMUXC_GPR13_SATA_PHY_2_MASK   (0x1f<<2)
 #define IOMUXC_GPR13_SATA_PHY_1_MASK   (3<<0)
 
+#define IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK (0x3 << 17)
+#define IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC_MASK    (IOMUX_GPR1_FEC_CLOCK_MUX1_SEL_MASK \
+                               | IOMUX_GPR1_FEC_CLOCK_MUX2_SEL_MASK)
+
+#define IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK (0x1 << 17)
+#define IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK (0x1 << 13)
+#define IOMUX_GPR1_FEC1_MASK   (IOMUX_GPR1_FEC1_CLOCK_MUX1_SEL_MASK \
+                               | IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK)
+
+#define IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK (0x1 << 18)
+#define IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK (0x1 << 14)
+#define IOMUX_GPR1_FEC2_MASK   (IOMUX_GPR1_FEC2_CLOCK_MUX1_SEL_MASK \
+                               | IOMUX_GPR1_FEC2_CLOCK_MUX2_SEL_MASK)
+
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_0P5DB     (0<<24)
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P0DB     (1<<24)
 #define IOMUXC_GPR13_SATA_PHY_8_RXEQ_1P5DB     (2<<24)
@@ -119,4 +176,17 @@
                                |IOMUXC_GPR13_SATA_PHY_3_MASK \
                                |IOMUXC_GPR13_SATA_PHY_2_MASK \
                                |IOMUXC_GPR13_SATA_PHY_1_MASK)
+
+/*
+ * Setup RGMII voltage levels on iMX6 SoC - the
+ *
+ * IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII - register
+ *
+ * 1P2V_IO - USB_HSIC, MIPI_HSI
+ * 1P5V_IO - ENET pins
+ */
+#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_RGMII   0x020e0790
+#define DDR_SEL_1P2V_IO (0x2 << 18)
+#define DDR_SEL_1P5V_IO (0x3 << 18)
+
 #endif /* __ASM_ARCH_IOMUX_H__ */