Merge branch 'ext4'

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index cad957a3b77283f6ab2e5d4988572b35eb576e07..8834c59dccefe40dbc4007dfbfa71ed73e74d22a 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -19,6 +19,10 @@
 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
 #define __ASM_ARCH_MX6_IMX_REGS_H__
 
+#define ARCH_MXC
+
+#define CONFIG_SYS_CACHELINE_SIZE      32
+
 #define ROMCP_ARB_BASE_ADDR             0x00000000
 #define ROMCP_ARB_END_ADDR              0x000FFFFF
 #define CAAM_ARB_BASE_ADDR              0x00100000
@@ -71,6 +75,9 @@
 #define MMDC1_ARB_BASE_ADDR             0x80000000
 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
 
+#define IPU_SOC_BASE_ADDR              IPU1_ARB_BASE_ADDR
+#define IPU_SOC_OFFSET                 0x00200000
+
 /* Defines for Blocks connected via AIPS (SkyBlue) */
 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
@@ -167,10 +174,6 @@
 #define IMX_IIM_BASE                 OCOTP_BASE_ADDR
 #define FEC_QUIRK_ENET_MAC
 
-#define GPIO_NUMBER(port, index)               ((((port)-1)*32)+((index)&31))
-#define GPIO_TO_PORT(number)           (((number)/32)+1)
-#define GPIO_TO_INDEX(number)          ((number)&31)
-
 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 #include <asm/types.h>
 
@@ -436,5 +439,35 @@ struct anatop_regs {
        u32     digprog;                /* 0x260 */
 };
 
+struct iomuxc_base_regs {
+       u32     gpr[14];        /* 0x000 */
+       u32     obsrv[5];       /* 0x038 */
+       u32     swmux_ctl[197]; /* 0x04c */
+       u32     swpad_ctl[250]; /* 0x360 */
+       u32     swgrp[26];      /* 0x748 */
+       u32     daisy[104];     /* 0x7b0..94c */
+};
+
+struct src_regs {
+       u32     scr;            /* 0x00 */
+       u32     sbmr1;          /* 0x04 */
+       u32     srsr;           /* 0x08 */
+       u32     reserved1;      /* 0x0c */
+       u32     reserved2;      /* 0x10 */
+       u32     sisr;           /* 0x14 */
+       u32     simr;           /* 0x18 */
+       u32     sbmr2;          /* 0x1c */
+       u32     gpr1;           /* 0x20 */
+       u32     gpr2;           /* 0x24 */
+       u32     gpr3;           /* 0x28 */
+       u32     gpr4;           /* 0x2c */
+       u32     gpr5;           /* 0x30 */
+       u32     gpr6;           /* 0x34 */
+       u32     gpr7;           /* 0x38 */
+       u32     gpr8;           /* 0x3c */
+       u32     gpr9;           /* 0x40 */
+       u32     gpr10;          /* 0x44 */
+};
+
 #endif /* __ASSEMBLER__*/
 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */