Merge branch 'master' of git://www.denx.de/git/u-boot-microblaze

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 5c45bf6d6e9fea2cfa13f1c737875a5a537eb5e6..53488bef552683f6d231763f004ed4d18fb1b8dd 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -162,6 +162,7 @@
 #endif
 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
+#define UART8_BASE                  (ATZ1_BASE_ADDR + 0x24000)
 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
@@ -356,6 +357,30 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
 
+struct rdc_regs {
+       u32     vir;            /* Version information */
+       u32     reserved1[8];
+       u32     stat;           /* Status */
+       u32     intctrl;        /* Interrupt and Control */
+       u32     intstat;        /* Interrupt Status */
+       u32     reserved2[116];
+       u32     mda[32];        /* Master Domain Assignment */
+       u32     reserved3[96];
+       u32     pdap[104];      /* Peripheral Domain Access Permissions */
+       u32     reserved4[88];
+       struct {
+               u32 mrsa;       /* Memory Region Start Address */
+               u32 mrea;       /* Memory Region End Address */
+               u32 mrc;        /* Memory Region Control */
+               u32 mrvs;       /* Memory Region Violation Status */
+       } mem_region[55];
+};
+
+struct rdc_sema_regs {
+       u8      gate[64];       /* Gate */
+       u16     rstgt;          /* Reset Gate */
+};
+
 /* WEIM registers */
 struct weim {
        u32 cs0gcr1;
@@ -414,6 +439,11 @@ struct src {
        u32     gpr10;
 };
 
+#define SRC_SCR_M4_ENABLE_OFFSET                22
+#define SRC_SCR_M4_ENABLE_MASK                  (1 << 22)
+#define SRC_SCR_M4C_NON_SCLR_RST_OFFSET         4
+#define SRC_SCR_M4C_NON_SCLR_RST_MASK           (1 << 4)
+
 /* GPR1 bitfields */
 #define IOMUXC_GPR1_APP_CLK_REQ_N              BIT(30)
 #define IOMUXC_GPR1_PCIE_EXIT_L1               BIT(28)