arm, imx6, i2c: add I2C4 for MX6DL

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx6 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 2631beb924ffdf821c43fb025a5f38fdf0001954..0d38d450daa8a37d80dfa9490e5dd948797c7f4c 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -88,14 +88,14 @@
 #define AIPS2_ARB_BASE_ADDR             0x02100000
 #define AIPS2_ARB_END_ADDR              0x021FFFFF
 #ifdef CONFIG_MX6SX
-#define AIPS3_BASE_ADDR                        0x02200000
-#define AIPS3_END_ADDR                 0x022FFFFF
+#define AIPS3_ARB_BASE_ADDR             0x02200000
+#define AIPS3_ARB_END_ADDR              0x022FFFFF
 #define WEIM_ARB_BASE_ADDR              0x50000000
 #define WEIM_ARB_END_ADDR               0x57FFFFFF
-#define QSPI1_ARB_BASE_ADDR             0x60000000
-#define QSPI1_ARB_END_ADDR              0x6FFFFFFF
-#define QSPI2_ARB_BASE_ADDR             0x70000000
-#define QSPI2_ARB_END_ADDR              0x7FFFFFFF
+#define QSPI0_AMBA_BASE                0x60000000
+#define QSPI0_AMBA_END                 0x6FFFFFFF
+#define QSPI1_AMBA_BASE                0x70000000
+#define QSPI1_AMBA_END                 0x7FFFFFFF
 #else
 #define SATA_ARB_BASE_ADDR              0x02200000
 #define SATA_ARB_END_ADDR               0x02203FFF
@@ -215,13 +215,12 @@
 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 #define ARM_BASE_ADDR              (ATZ2_BASE_ADDR + 0x40000)
-#ifdef CONFIG_MX6SL
-#define USBO2H_PL301_IPS_BASE_ADDR  (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBO2H_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
-#else
-#define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
-#define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
-#endif
+
+#define CONFIG_SYS_FSL_SEC_ADDR     CAAM_BASE_ADDR
+#define CONFIG_SYS_FSL_JR0_ADDR     (CAAM_BASE_ADDR + 0x1000)
+
+#define USB_PL301_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x0000)
+#define USB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x4000)
 
 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 #ifdef CONFIG_MX6SL
@@ -267,8 +266,8 @@
 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 #ifdef CONFIG_MX6SX
 #define SAI2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x5C000)
-#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
-#define QSPI2_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
+#define QSPI0_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x60000)
+#define QSPI1_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x64000)
 #else
 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
@@ -278,6 +277,7 @@
 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
+#define I2C4_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 
@@ -337,6 +337,43 @@ extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 #define SRC_SCR_CORE_3_ENABLE_OFFSET    24
 #define SRC_SCR_CORE_3_ENABLE_MASK      (1<<SRC_SCR_CORE_3_ENABLE_OFFSET)
 
+/* WEIM registers */
+struct weim {
+       u32 cs0gcr1;
+       u32 cs0gcr2;
+       u32 cs0rcr1;
+       u32 cs0rcr2;
+       u32 cs0wcr1;
+       u32 cs0wcr2;
+
+       u32 cs1gcr1;
+       u32 cs1gcr2;
+       u32 cs1rcr1;
+       u32 cs1rcr2;
+       u32 cs1wcr1;
+       u32 cs1wcr2;
+
+       u32 cs2gcr1;
+       u32 cs2gcr2;
+       u32 cs2rcr1;
+       u32 cs2rcr2;
+       u32 cs2wcr1;
+       u32 cs2wcr2;
+
+       u32 cs3gcr1;
+       u32 cs3gcr2;
+       u32 cs3rcr1;
+       u32 cs3rcr2;
+       u32 cs3wcr1;
+       u32 cs3wcr2;
+
+       u32 unused[12];
+
+       u32 wcr;
+       u32 wiar;
+       u32 ear;
+};
+
 /* System Reset Controller (SRC) */
 struct src {
        u32     scr;
@@ -419,6 +456,19 @@ struct iomuxc {
        u32 gpr[14];
 };
 
+struct gpc {
+       u32     cntr;
+       u32     pgr;
+       u32     imr1;
+       u32     imr2;
+       u32     imr3;
+       u32     imr4;
+       u32     isr1;
+       u32     isr2;
+       u32     isr3;
+       u32     isr4;
+};
+
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET           20
 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK             (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET              16
@@ -579,12 +629,35 @@ struct fuse_bank0_regs {
        u32     rsvd1[3];
        u32     uid_high;
        u32     rsvd2[3];
-       u32     rsvd3[4];
-       u32     rsvd4[4];
-       u32     rsvd5[4];
+       u32     cfg2;
+       u32     rsvd3[3];
+       u32     cfg3;
+       u32     rsvd4[3];
+       u32     cfg4;
+       u32     rsvd5[3];
        u32     cfg5;
        u32     rsvd6[3];
-       u32     rsvd7[4];
+       u32     cfg6;
+       u32     rsvd7[3];
+};
+
+struct fuse_bank1_regs {
+       u32     mem0;
+       u32     rsvd0[3];
+       u32     mem1;
+       u32     rsvd1[3];
+       u32     mem2;
+       u32     rsvd2[3];
+       u32     mem3;
+       u32     rsvd3[3];
+       u32     mem4;
+       u32     rsvd4[3];
+       u32     ana0;
+       u32     rsvd5[3];
+       u32     ana1;
+       u32     rsvd6[3];
+       u32     ana2;
+       u32     rsvd7[3];
 };
 
 #ifdef CONFIG_MX6SX