ARM: DRA7: Add support for IO delay configuration

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx6 / crm_regs.h

diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h
index 0fcef69768e792ce12642fca477b4bf9b58b033f..887d04850f63f242948298dff167d41ad7b1c8be 100644 (file)
--- a/arch/arm/include/asm/arch-mx6/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx6/crm_regs.h
@@ -89,7 +89,7 @@ struct mxc_ccm_reg {
        u32 analog_pll_video_tog;
        u32 analog_pll_video_num;               /* 0x40b0 */
        u32 analog_reserved6[3];
-       u32 analog_pll_vedio_denon;             /* 0x40c0 */
+       u32 analog_pll_video_denom;             /* 0x40c0 */
        u32 analog_reserved7[7];
        u32 analog_pll_enet;                    /* 0x40e0 */
        u32 analog_pll_enet_set;
@@ -228,6 +228,8 @@ struct mxc_ccm_reg {
 #ifdef CONFIG_MX6SX
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK              (0x7 << 7)
 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET            7
+#endif
+#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK                        (1 << 6)
 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET              6
 #endif
@@ -335,8 +337,8 @@ struct mxc_ccm_reg {
 #endif
 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK             (0x7 << 25)
 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET           25
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK             (0x7 << 19)
-#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET           19
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK             (0x7 << 22)
+#define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET           22
 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK              (0x3 << 20)
 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET            20
 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK             (0x7 << 12)
@@ -432,7 +434,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS              (1 << 19)
 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM                   (1 << 17)
 #endif
-#define MXC_CCM_CLPCR_WB_PER_AT_LPM                    (1 << 17)
+#define MXC_CCM_CLPCR_WB_PER_AT_LPM                    (1 << 16)
 #define MXC_CCM_CLPCR_COSC_PWRDOWN                     (1 << 11)
 #define MXC_CCM_CLPCR_STBY_COUNT_MASK                  (0x3 << 9)
 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET                        9
@@ -469,7 +471,7 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED                (1 << 22)
 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED         (1 << 21)
 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED              (1 << 20)
-#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED       (1 << 22)
+#define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED       (1 << 19)
 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED              (1 << 17)
 #define MXC_CCM_CIMR_MASK_COSC_READY                   (1 << 6)
 #define MXC_CCM_CIMR_MASK_LRF_PLL                      1
@@ -590,6 +592,8 @@ struct mxc_ccm_reg {
 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET               10
 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK                 (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
+#define MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET               8
+#define MXC_CCM_CCGR1_I2C4_SERIAL_MASK                 (3 << MXC_CCM_CCGR1_I2C4_SERIAL_OFFSET)
 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET                        12
 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK                  (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET          14
@@ -931,10 +935,10 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PLL_VIDEO_RSVD0(v)  \
        (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
-#define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT      19
-#define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
-#define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v)  \
-       (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
+#define BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT      19
+#define BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT 0x00180000
+#define BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(v)  \
+       (((v) << 19) & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT)
 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
@@ -981,6 +985,7 @@ struct mxc_ccm_reg {
 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
 #define BF_ANADIG_PLL_ENET_RSVD1(v)  \
        (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
+#define BM_ANADIG_PLL_ENET_REF_25M_ENABLE 0x00200000
 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
@@ -1060,4 +1065,6 @@ struct mxc_ccm_reg {
 #define BF_ANADIG_PFD_528_PFD0_FRAC(v)  \
        (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
 
+#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
+
 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */