Merge branch 'master' of git://git.denx.de/u-boot-nand-flash

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx5 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx5/imx-regs.h b/arch/arm/include/asm/arch-mx5/imx-regs.h
index d069209b587e9213961dfae6c521f787ef07d478..4fa66587a0b7dabdd9a76ba0dd7aaf02a47d5882 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -54,7 +54,7 @@
  */
 #define MMC_SDHC1_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00004000)
 #define MMC_SDHC2_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00008000)
-#define UART3_BASE_ADDR        (SPBA0_BASE_ADDR + 0x0000C000)
+#define UART3_BASE             (SPBA0_BASE_ADDR + 0x0000C000)
 #define CSPI1_BASE_ADDR        (SPBA0_BASE_ADDR + 0x00010000)
 #define SSI2_BASE_ADDR         (SPBA0_BASE_ADDR + 0x00014000)
 #define MMC_SDHC3_BASE_ADDR    (SPBA0_BASE_ADDR + 0x00020000)
@@ -83,8 +83,8 @@
 #define EPIT2_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000B0000)
 #define PWM1_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B4000)
 #define PWM2_BASE_ADDR         (AIPS1_BASE_ADDR + 0x000B8000)
-#define UART1_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000BC000)
-#define UART2_BASE_ADDR                (AIPS1_BASE_ADDR + 0x000C0000)
+#define UART1_BASE             (AIPS1_BASE_ADDR + 0x000BC000)
+#define UART2_BASE             (AIPS1_BASE_ADDR + 0x000C0000)
 #define SRC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D0000)
 #define CCM_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D4000)
 #define GPC_BASE_ADDR          (AIPS1_BASE_ADDR + 0x000D8000)
@@ -222,6 +222,36 @@
 #define CS0_64M_CS1_32M_CS2_32M                        2
 #define CS0_32M_CS1_32M_CS2_32M_CS3_32M                3
 
+/*
+ * CSPI register definitions
+ */
+#define MXC_ECSPI
+#define MXC_CSPICTRL_EN                (1 << 0)
+#define MXC_CSPICTRL_MODE      (1 << 1)
+#define MXC_CSPICTRL_XCH       (1 << 2)
+#define MXC_CSPICTRL_CHIPSELECT(x)     (((x) & 0x3) << 12)
+#define MXC_CSPICTRL_BITCOUNT(x)       (((x) & 0xfff) << 20)
+#define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
+#define MXC_CSPICTRL_POSTDIV(x)        (((x) & 0xF) << 8)
+#define MXC_CSPICTRL_SELCHAN(x)        (((x) & 0x3) << 18)
+#define MXC_CSPICTRL_MAXBITS   0xfff
+#define MXC_CSPICTRL_TC                (1 << 7)
+#define MXC_CSPICTRL_RXOVF     (1 << 6)
+#define MXC_CSPIPERIOD_32KHZ   (1 << 15)
+#define MAX_SPI_BYTES  32
+
+/* Bit position inside CTRL register to be associated with SS */
+#define MXC_CSPICTRL_CHAN      18
+
+/* Bit position inside CON register to be associated with SS */
+#define MXC_CSPICON_POL                4
+#define MXC_CSPICON_PHA                0
+#define MXC_CSPICON_SSPOL      12
+#define MXC_SPI_BASE_ADDRESSES \
+       CSPI1_BASE_ADDR, \
+       CSPI2_BASE_ADDR, \
+       CSPI3_BASE_ADDR,
+
 /*
  * Number of GPIO pins per port
  */