imx25: Add new hardware registers

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx5 / crm_regs.h

diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h
index d5eb3033884dca6c4fc90785af49d7f8ccfca371..efe57e07ea31c39f2196817c2f8aedf59fde8d84 100644 (file)
--- a/arch/arm/include/asm/arch-mx5/crm_regs.h
+++ b/arch/arm/include/asm/arch-mx5/crm_regs.h
@@ -1,23 +1,7 @@
 /*
  * (C) Copyright 2009 Freescale Semiconductor, Inc.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef __ARCH_ARM_MACH_MX51_CRM_REGS_H__
@@ -82,6 +66,44 @@ struct mxc_ccm_reg {
        u32 cmeor;
 };
 
+/* Define the bits in register CCR */
+#define MXC_CCM_CCR_COSC_EN                    (0x1 << 12)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_MULT                   (0x1 << 11)
+#endif
+#define MXC_CCM_CCR_CAMP2_EN                   (0x1 << 10)
+#define MXC_CCM_CCR_CAMP1_EN                   (0x1 << 9)
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCR_FPM_EN                     (0x1 << 8)
+#endif
+#define MXC_CCM_CCR_OSCNT_OFFSET               0
+#define MXC_CCM_CCR_OSCNT_MASK                 0xFF
+#define MXC_CCM_CCR_OSCNT(v)                   ((v) & 0xFF)
+#define MXC_CCM_CCR_OSCNT_RD(r)                        ((r) & 0xFF)
+
+/* Define the bits in register CCSR */
+#if defined(CONFIG_MX51)
+#define MXC_CCM_CCSR_LP_APM                    (0x1 << 9)
+#elif defined(CONFIG_MX53)
+#define MXC_CCM_CCSR_LP_APM                    (0x1 << 10)
+#define MXC_CCM_CCSR_PLL4_SW_CLK_SEL           (0x1 << 9)
+#endif
+#define MXC_CCM_CCSR_STEP_SEL_OFFSET           7
+#define MXC_CCM_CCSR_STEP_SEL_MASK             (0x3 << 7)
+#define MXC_CCM_CCSR_STEP_SEL(v)               (((v) & 0x3) << 7)
+#define MXC_CCM_CCSR_STEP_SEL_RD(r)            (((r) >> 7) & 0x3)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_OFFSET      5
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_MASK                (0x3 << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF(v)          (((v) & 0x3) << 5)
+#define MXC_CCM_CCSR_PLL2_DIV_PODF_RD(r)       (((r) >> 5) & 0x3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_OFFSET      3
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_MASK                (0x3 << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF(v)          (((v) & 0x3) << 3)
+#define MXC_CCM_CCSR_PLL3_DIV_PODF_RD(r)       (((r) >> 3) & 0x3)
+#define MXC_CCM_CCSR_PLL1_SW_CLK_SEL           (0x1 << 2)
+#define MXC_CCM_CCSR_PLL2_SW_CLK_SEL           (0x1 << 1)
+#define MXC_CCM_CCSR_PLL3_SW_CLK_SEL           0x1
+
 /* Define the bits in register CACRR */
 #define MXC_CCM_CACRR_ARM_PODF_OFFSET          0
 #define MXC_CCM_CACRR_ARM_PODF_MASK            0x7
@@ -283,8 +305,14 @@ struct mxc_ccm_reg {
 /* Define the bits in register CCDR */
 #define MXC_CCM_CCDR_IPU_HS_MASK                       (0x1 << 17)
 
+/* Define the bits in register CGPR */
+#define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE            (1 << 4)
+
 /* Define the bits in register CCGRx */
 #define MXC_CCM_CCGR_CG_MASK                           0x3
+#define MXC_CCM_CCGR_CG_OFF                            0x0
+#define MXC_CCM_CCGR_CG_RUN_ON                         0x1
+#define MXC_CCM_CCGR_CG_ON                             0x3
 
 #define MXC_CCM_CCGR0_ARM_BUS_OFFSET                   0
 #define MXC_CCM_CCGR0_ARM_BUS(v)                       (((v) & 0x3) << 0)