Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

[oweals/u-boot.git] / arch / arm / include / asm / arch-mx25 / imx-regs.h

diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h
index 2ccb445975950c21b1ff6c565dc81208b53c20c4..7f9449b2d0659a3614b9cadf4a5784e7de554c1f 100644 (file)
--- a/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -36,7 +36,6 @@
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_FEC_MXC
 extern void mx25_fec_init_pins(void);
-extern void imx_get_mac_from_fuse(unsigned char *mac);
 #endif
 
 /* Clock Control Module (CCM) registers */
@@ -84,18 +83,6 @@ struct esdramc_regs {
        u32 cdlyl;      /* delay line cycle length debug */
 };
 
-/* GPIO registers */
-struct gpio_regs {
-       u32 gpio_dr;    /* data */
-       u32 gpio_dir;   /* direction */
-       u32 psr;        /* pad satus */
-       u32 icr1;       /* interrupt config 1 */
-       u32 icr2;       /* interrupt config 2 */
-       u32 imr;        /* interrupt mask */
-       u32 isr;        /* interrupt status */
-       u32 edge_sel;   /* edge select */
-};
-
 /* General Purpose Timer (GPT) registers */
 struct gpt_regs {
        u32 ctrl;       /* control */
@@ -193,8 +180,8 @@ struct aips_regs {
 #define IMX_I2C3_BASE          (0x43F84000)
 #define IMX_CAN1_BASE          (0x43F88000)
 #define IMX_CAN2_BASE          (0x43F8C000)
-#define IMX_UART1_BASE         (0x43F90000)
-#define IMX_UART2_BASE         (0x43F94000)
+#define UART1_BASE             (0x43F90000)
+#define UART2_BASE             (0x43F94000)
 #define IMX_I2C2_BASE          (0x43F98000)
 #define IMX_OWIRE_BASE         (0x43F9C000)
 #define IMX_CSPI1_BASE         (0x43FA4000)
@@ -210,15 +197,15 @@ struct aips_regs {
 /* SPBA */
 #define IMX_SPBA_BASE          (0x50000000)
 #define IMX_CSPI3_BASE         (0x50004000)
-#define IMX_UART4_BASE         (0x50008000)
-#define IMX_UART3_BASE         (0x5000C000)
+#define UART4_BASE             (0x50008000)
+#define UART3_BASE             (0x5000C000)
 #define IMX_CSPI2_BASE         (0x50010000)
 #define IMX_SSI2_BASE          (0x50014000)
 #define IMX_ESAI_BASE          (0x50018000)
 #define IMX_ATA_DMA_BASE       (0x50020000)
 #define IMX_SIM1_BASE          (0x50024000)
 #define IMX_SIM2_BASE          (0x50028000)
-#define IMX_UART5_BASE         (0x5002C000)
+#define UART5_BASE             (0x5002C000)
 #define IMX_TSC_BASE           (0x50030000)
 #define IMX_SSI1_BASE          (0x50034000)
 #define IMX_FEC_BASE           (0x50038000)
@@ -363,4 +350,7 @@ struct aips_regs {
 #define GPIO3_BASE_ADDR                IMX_GPIO3_BASE
 #define GPIO4_BASE_ADDR                IMX_GPIO4_BASE
 
+#define CHIP_REV_1_0           0x10
+#define CHIP_REV_1_1           0x11
+
 #endif                         /* _IMX_REGS_H */