Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-lsch3 / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
index dd11ef79c8c2f2f97a38f35d98b9f4d9f07050a1..d6bee60385f04d8dee260dbb7a699a6ec38ffb8b 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/immap_lsch3.h
@@ -47,6 +47,30 @@ struct ccsr_gur {
        u32     devdisr5;       /* Device disable control 5 */
        u32     devdisr6;       /* Device disable control 6 */
        u32     devdisr7;       /* Device disable control 7 */
+#define FSL_CHASSIS3_DEVDISR2_DPMAC1   0x00000001
+#define FSL_CHASSIS3_DEVDISR2_DPMAC2   0x00000002
+#define FSL_CHASSIS3_DEVDISR2_DPMAC3   0x00000004
+#define FSL_CHASSIS3_DEVDISR2_DPMAC4   0x00000008
+#define FSL_CHASSIS3_DEVDISR2_DPMAC5   0x00000010
+#define FSL_CHASSIS3_DEVDISR2_DPMAC6   0x00000020
+#define FSL_CHASSIS3_DEVDISR2_DPMAC7   0x00000040
+#define FSL_CHASSIS3_DEVDISR2_DPMAC8   0x00000080
+#define FSL_CHASSIS3_DEVDISR2_DPMAC9   0x00000100
+#define FSL_CHASSIS3_DEVDISR2_DPMAC10  0x00000200
+#define FSL_CHASSIS3_DEVDISR2_DPMAC11  0x00000400
+#define FSL_CHASSIS3_DEVDISR2_DPMAC12  0x00000800
+#define FSL_CHASSIS3_DEVDISR2_DPMAC13  0x00001000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC14  0x00002000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC15  0x00004000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC16  0x00008000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC17  0x00010000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC18  0x00020000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC19  0x00040000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC20  0x00080000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC21  0x00100000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC22  0x00200000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC23  0x00400000
+#define FSL_CHASSIS3_DEVDISR2_DPMAC24  0x00800000
        u8      res_08c[0x90-0x8c];
        u32     coredisru;      /* uppper portion for support of 64 cores */
        u32     coredisrl;      /* lower portion for support of 64 cores */
@@ -63,6 +87,11 @@ struct ccsr_gur {
 #define FSL_CHASSIS3_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_SHIFT 18
 #define FSL_CHASSIS3_RCWSR0_MEM2_PLL_RAT_MASK  0x3f
+#define        FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK   0x00FF0000
+#define        FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
+#define        FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
+#define        FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
+
        u8      res_180[0x200-0x180];
        u32     scratchrw[32];  /* Scratch Read/Write */
        u8      res_280[0x300-0x280];