colibri_vf: Enable board specific USB initialisation for USB pen gpio

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-lsch3 / config.h

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index b140c1fac2c2d51fb43ea2157ddec7f3a4b60c20..ca8d38cf78b720b02f04996a57c2ace698a5fc58 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -8,6 +8,14 @@
 #define _ASM_ARMV8_FSL_LSCH3_CONFIG_
 
 #include <fsl_ddrc_version.h>
+
+#define CONFIG_SYS_PAGE_SIZE           0x10000
+
+#ifndef L1_CACHE_BYTES
+#define L1_CACHE_SHIFT         6
+#define L1_CACHE_BYTES         (1 << L1_CACHE_SHIFT)
+#endif
+
 #define CONFIG_MP
 #define CONFIG_SYS_FSL_OCRAM_BASE      0x18000000      /* initial RAM */
 /* Link Definitions */
@@ -23,6 +31,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR       (CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR       (CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR       (CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1                        (CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011C0600)
@@ -30,6 +39,20 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR             (CONFIG_SYS_FSL_PMU_ADDR + \
                                                 0x18A0)
 
+#define CONFIG_SYS_FSL_WRIOP1_ADDR             (CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
+#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR       (CONFIG_SYS_IMMR + 0xEA0000)
+
+/* SP (Cortex-A5) related */
+#define CONFIG_SYS_FSL_SP_ADDR                 (CONFIG_SYS_IMMR + 0x00F00000)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR         (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1                (CONFIG_SYS_FSL_SP_ADDR)
+#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2                \
+                                       (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
+#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART       \
+                                       (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
+
 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR           0x70012c000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR          0x70012d000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR          0x700132000ULL
@@ -88,22 +111,57 @@
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
 
-
+#define CONFIG_SYS_FSL_ESDHC_LE
 /* IFC */
 #define CONFIG_SYS_FSL_IFC_LE
+#define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
+
+/* PCIe */
+#define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
+#define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
+#define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
+#define CONFIG_SYS_PCIE4_ADDR                  (CONFIG_SYS_IMMR + 0x2700000)
+#define CONFIG_SYS_PCIE1_PHYS_ADDR             0x1000000000ULL
+#define CONFIG_SYS_PCIE2_PHYS_ADDR             0x1200000000ULL
+#define CONFIG_SYS_PCIE3_PHYS_ADDR             0x1400000000ULL
+#define CONFIG_SYS_PCIE4_PHYS_ADDR             0x1600000000ULL
+
+/* Cache Coherent Interconnect */
+#define CCI_MN_BASE            0x04000000
+#define CCI_MN_RNF_NODEID_LIST         0x180
+#define CCI_MN_DVM_DOMAIN_CTL          0x200
+#define CCI_MN_DVM_DOMAIN_CTL_SET      0x210
+
+/* Device Configuration */
+#define DCFG_BASE              0x01e00000
+#define DCFG_PORSR1                    0x000
+#define DCFG_PORSR1_RCW_SRC            0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR                0x12f00000
+
+#define DCFG_DCSR_BASE         0X700100000ULL
+#define DCFG_DCSR_PORCR1               0x000
+
+/* Supplemental Configuration */
+#define SCFG_BASE              0x01fc0000
+#define SCFG_USB3PRM1CR                        0x000
 
 #ifdef CONFIG_LS2085A
 #define CONFIG_MAX_CPUS                                16
 #define CONFIG_SYS_FSL_IFC_BANK_COUNT          8
 #define CONFIG_NUM_DDR_CONTROLLERS             3
 #define CONFIG_SYS_FSL_CLUSTER_CLOCKS          { 1, 1, 4, 4 }
+#define CONFIG_SYS_FSL_SRDS_1
+#define CONFIG_SYS_FSL_SRDS_2
 #else
 #error SoC not defined
 #endif
 
 #ifdef CONFIG_LS2085A
 #define CONFIG_SYS_FSL_ERRATUM_A008336
+#define CONFIG_SYS_FSL_ERRATUM_A008511
 #define CONFIG_SYS_FSL_ERRATUM_A008514
+#define CONFIG_SYS_FSL_ERRATUM_A008585
+#define CONFIG_SYS_FSL_ERRATUM_A008751
 #endif
 
 #endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */