colibri_vf: Enable board specific USB initialisation for USB pen gpio

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-lsch3 / config.h

diff --git a/arch/arm/include/asm/arch-fsl-lsch3/config.h b/arch/arm/include/asm/arch-fsl-lsch3/config.h
index 684c70f20ee5d3d96bd3188512cba1138d277f35..ca8d38cf78b720b02f04996a57c2ace698a5fc58 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-lsch3/config.h
+++ b/arch/arm/include/asm/arch-fsl-lsch3/config.h
@@ -31,6 +31,7 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR       (CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR       (CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR       (CONFIG_SYS_IMMR + 0x00370000)
+#define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1                        (CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011C0600)
@@ -38,6 +39,9 @@
 #define CONFIG_SYS_FSL_PMU_CLTBENR             (CONFIG_SYS_FSL_PMU_ADDR + \
                                                 0x18A0)
 
+#define CONFIG_SYS_FSL_WRIOP1_ADDR             (CONFIG_SYS_IMMR + 0x7B80000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO1    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
+#define CONFIG_SYS_FSL_WRIOP1_MDIO2    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR       (CONFIG_SYS_IMMR + 0xEA0000)
 
 /* SP (Cortex-A5) related */
@@ -107,6 +111,7 @@
 #define CONFIG_MAX_MEM_MAPPED          CONFIG_SYS_LS2_DDR_BLOCK1_SIZE
 #define CONFIG_SYS_FSL_DDR_VER         FSL_DDR_VER_5_0
 
+#define CONFIG_SYS_FSL_ESDHC_LE
 /* IFC */
 #define CONFIG_SYS_FSL_IFC_LE
 #define CONFIG_SYS_MEMAC_LITTLE_ENDIAN
@@ -127,6 +132,15 @@
 #define CCI_MN_DVM_DOMAIN_CTL          0x200
 #define CCI_MN_DVM_DOMAIN_CTL_SET      0x210
 
+/* Device Configuration */
+#define DCFG_BASE              0x01e00000
+#define DCFG_PORSR1                    0x000
+#define DCFG_PORSR1_RCW_SRC            0xff800000
+#define DCFG_PORSR1_RCW_SRC_NOR                0x12f00000
+
+#define DCFG_DCSR_BASE         0X700100000ULL
+#define DCFG_DCSR_PORCR1               0x000
+
 /* Supplemental Configuration */
 #define SCFG_BASE              0x01fc0000
 #define SCFG_USB3PRM1CR                        0x000