armv8/fsl-lsch2: refactor the clock system initialization

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / soc.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/soc.h b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
index 4512732f79908a24752f85f13784f619dc1b3aaf..78363b602c778f74a67832bd6be64ef32fe3202d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/soc.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/soc.h
@@ -30,7 +30,7 @@
 #define pex_lut_in32(a)       in_be32(a)
 #define pex_lut_out32(a, v)   out_be32(a, v)
 #endif
-
+#ifndef __ASSEMBLY__
 struct cpu_type {
        char name[15];
        u32 soc_ver;
@@ -39,7 +39,7 @@ struct cpu_type {
 
 #define CPU_TYPE_ENTRY(n, v, nc) \
        { .name = #n, .soc_ver = SVR_##v, .num_cores = (nc)}
-
+#endif
 #define SVR_WO_E               0xFFFFFE
 #define SVR_LS1012A            0x870400
 #define SVR_LS1043A            0x879200
@@ -50,6 +50,12 @@ struct cpu_type {
 #define SVR_LS2080A            0x870110
 #define SVR_LS2085A            0x870100
 #define SVR_LS2040A            0x870130
+#define SVR_LS2088A            0x870900
+#define SVR_LS2084A            0x870910
+#define SVR_LS2048A            0x870920
+#define SVR_LS2044A            0x870930
+
+#define SVR_DEV_LS2080A                0x8701
 
 #define SVR_MAJ(svr)           (((svr) >> 4) & 0xf)
 #define SVR_MIN(svr)           (((svr) >> 0) & 0xf)
@@ -60,10 +66,10 @@ struct cpu_type {
 
 /* ahci port register default value */
 #define AHCI_PORT_PHY_1_CFG    0xa003fffe
-#define AHCI_PORT_PHY_2_CFG    0x28184d1f
-#define AHCI_PORT_PHY_3_CFG    0x0e081509
 #define AHCI_PORT_TRANS_CFG    0x08000029
+#define AHCI_PORT_AXICC_CFG    0x3fffffff
 
+#ifndef __ASSEMBLY__
 /* AHCI (sata) register map */
 struct ccsr_ahci {
        u32 res1[0xa4/4];       /* 0x0 - 0xa4 */
@@ -106,4 +112,5 @@ void erratum_a010315(void);
 
 bool soc_has_dp_ddr(void);
 bool soc_has_aiop(void);
+#endif
 #endif /* _ASM_ARMV8_FSL_LAYERSCAPE_SOC_H_ */