Merge git://git.denx.de/u-boot-samsung

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 91f3ce843ad492565afcac00307e9bd2a3425301..e18dcbdd0900348281a9042d4ff16d637020cc90 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -19,28 +19,23 @@
 #define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR       (CONFIG_SYS_IMMR + 0x00300000)
 #define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR       (CONFIG_SYS_IMMR + 0x00310000)
 #define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR       (CONFIG_SYS_IMMR + 0x00370000)
+#define SYS_FSL_QSPI_ADDR                      (CONFIG_SYS_IMMR + 0x010c0000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x01140000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x01240000)
 #define CONFIG_SYS_NS16550_COM1                        (CONFIG_SYS_IMMR + 0x011C0500)
 #define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011C0600)
-#define CONFIG_SYS_FSL_TIMER_ADDR              0x023d0000
+#define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR     0x023d0000
+#define CONFIG_SYS_FSL_TIMER_ADDR              0x023e0000
 #define CONFIG_SYS_FSL_PMU_CLTBENR             (CONFIG_SYS_FSL_PMU_ADDR + \
                                                 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
+#define FSL_LSCH3_SVR          (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR             (CONFIG_SYS_IMMR + 0x7B80000)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO2    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR       (CONFIG_SYS_IMMR + 0xEA0000)
 
-/* SP (Cortex-A5) related */
-#define CONFIG_SYS_FSL_SP_ADDR                 (CONFIG_SYS_IMMR + 0x00F00000)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR         (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1                (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2                \
-                                       (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
-#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART       \
-                                       (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
-
 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR           0x70012c000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR          0x70012d000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR          0x700132000ULL
@@ -51,8 +46,8 @@
 #define I2C3_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01030000)
 
-#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR      (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR      (CONFIG_SYS_IMMR + 0x02110000)
+#define CONFIG_SYS_XHCI_USB1_ADDR              (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_XHCI_USB2_ADDR              (CONFIG_SYS_IMMR + 0x02110000)
 
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE                    0x01100000      /* as per CCSR map. */
@@ -73,6 +68,36 @@
 #define AHCI_BASE_ADDR1                                (CONFIG_SYS_IMMR + 0x02200000)
 #define AHCI_BASE_ADDR2                                (CONFIG_SYS_IMMR + 0x02210000)
 
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR            (CONFIG_SYS_IMMR + 0x00e80200)
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_OFFSET              0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET              0x07010000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR                (CONFIG_SYS_IMMR + 0x00e90000)
+
+/* MMU 500 */
+#define SMMU_SCR0                      (SMMU_BASE + 0x0)
+#define SMMU_SCR1                      (SMMU_BASE + 0x4)
+#define SMMU_SCR2                      (SMMU_BASE + 0x8)
+#define SMMU_SACR                      (SMMU_BASE + 0x10)
+#define SMMU_IDR0                      (SMMU_BASE + 0x20)
+#define SMMU_IDR1                      (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0                     (SMMU_BASE + 0x400)
+#define SMMU_NSCR2                     (SMMU_BASE + 0x408)
+#define SMMU_NSACR                     (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK             0x00000001
+#define SCR0_USFCFG_MASK               0x00000400
+
+
 /* PCIe */
 #define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
@@ -86,6 +111,10 @@
 #define PCIE_LUT_BASE                          0x80000
 #define PCIE_LUT_LCTRL0                                0x7F8
 #define PCIE_LUT_DBG                           0x7FC
+#define PCIE_LUT_UDR(n)         (0x800 + (n) * 8)
+#define PCIE_LUT_LDR(n)         (0x804 + (n) * 8)
+#define PCIE_LUT_ENABLE         (1 << 31)
+#define PCIE_LUT_ENTRY_COUNT    32
 
 /* Device Configuration */
 #define DCFG_BASE              0x01e00000
@@ -94,13 +123,21 @@
 #define DCFG_PORSR1_RCW_SRC_NOR                0x12f00000
 #define DCFG_RCWSR13                   0x130
 #define DCFG_RCWSR13_DSPI              (0 << 8)
+#define DCFG_RCWSR15                   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE         0X700100000ULL
 #define DCFG_DCSR_PORCR1               0x000
 
+/* Interrupt Sampling Control */
+#define ISC_BASE               0x01F70000
+#define IRQCR_OFFSET           0x14
+
 /* Supplemental Configuration */
 #define SCFG_BASE              0x01fc0000
 #define SCFG_USB3PRM1CR                        0x000
+#define SCFG_USB3PRM1CR_INIT           0x27672b2a
+#define SCFG_QSPICLKCTLR       0x10
 
 #define TP_ITYP_AV             0x00000001      /* Initiator available */
 #define TP_ITYP_TYPE(x)        (((x) & 0x6) >> 1)      /* Initiator Type */
@@ -113,12 +150,13 @@
 #define TY_ITYP_VER_A7         0x1
 #define TY_ITYP_VER_A53                0x2
 #define TY_ITYP_VER_A57                0x3
+#define TY_ITYP_VER_A72                0x4
 
 #define TP_CLUSTER_EOC         0x80000000      /* end of clusters */
 #define TP_CLUSTER_INIT_MASK   0x0000003f      /* initiator mask */
 #define TP_INIT_PER_CLUSTER     4
 /* This is chassis generation 3 */
-
+#ifndef __ASSEMBLY__
 struct sys_info {
        unsigned long freq_processor[CONFIG_MAX_CPUS];
        unsigned long freq_systembus;
@@ -146,6 +184,10 @@ struct ccsr_gur {
        u8      res_008[0x20-0x8];
        u32     gpporcr1;       /* General-purpose POR configuration */
        u32     gpporcr2;       /* General-purpose POR configuration 2 */
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT     25
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK      0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  20
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK   0x1F
        u32     dcfg_fusesr;    /* Fuse status register */
        u32     gpporcr3;
        u32     gpporcr4;
@@ -201,6 +243,8 @@ struct ccsr_gur {
 #define        FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
 #define        FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
 #define        FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
+#define RCW_SB_EN_REG_INDEX    9
+#define RCW_SB_EN_MASK         0x00000400
 
        u8      res_180[0x200-0x180];
        u32     scratchrw[32];  /* Scratch Read/Write */
@@ -275,4 +319,6 @@ struct ccsr_reset {
        u32 ip_rev1;                    /* 0xbf8 */
        u32 ip_rev2;                    /* 0xbfc */
 };
+
+#endif /*__ASSEMBLY__*/
 #endif /* __ARCH_FSL_LSCH3_IMMAP_H_ */