Merge git://git.denx.de/u-boot-dm

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 9b60bd310a6ae8e4cf7205ca43a46fd64b4c5b99..7acba2730aac21e861161f14de9904c522fd759d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -26,21 +26,13 @@
 #define CONFIG_SYS_FSL_TIMER_ADDR              0x023d0000
 #define CONFIG_SYS_FSL_PMU_CLTBENR             (CONFIG_SYS_FSL_PMU_ADDR + \
                                                 0x18A0)
+#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0)
 
 #define CONFIG_SYS_FSL_WRIOP1_ADDR             (CONFIG_SYS_IMMR + 0x7B80000)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO1    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000)
 #define CONFIG_SYS_FSL_WRIOP1_MDIO2    (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000)
 #define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR       (CONFIG_SYS_IMMR + 0xEA0000)
 
-/* SP (Cortex-A5) related */
-#define CONFIG_SYS_FSL_SP_ADDR                 (CONFIG_SYS_IMMR + 0x00F00000)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_ADDR         (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR1                (CONFIG_SYS_FSL_SP_ADDR)
-#define CONFIG_SYS_FSL_SP_VSG_GIC_VIGR2                \
-                                       (CONFIG_SYS_FSL_SP_ADDR + 0x0008)
-#define CONFIG_SYS_FSL_SP_LOOPBACK_DUART       \
-                                       (CONFIG_SYS_FSL_SP_ADDR + 0x1000)
-
 #define CONFIG_SYS_FSL_DCSR_DDR_ADDR           0x70012c000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR2_ADDR          0x70012d000ULL
 #define CONFIG_SYS_FSL_DCSR_DDR3_ADDR          0x700132000ULL
@@ -51,8 +43,8 @@
 #define I2C3_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01020000)
 #define I2C4_BASE_ADDR                         (CONFIG_SYS_IMMR + 0x01030000)
 
-#define CONFIG_SYS_LS2080A_XHCI_USB1_ADDR      (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_LS2080A_XHCI_USB2_ADDR      (CONFIG_SYS_IMMR + 0x02110000)
+#define CONFIG_SYS_XHCI_USB1_ADDR              (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_XHCI_USB2_ADDR              (CONFIG_SYS_IMMR + 0x02110000)
 
 /* TZ Address Space Controller Definitions */
 #define TZASC1_BASE                    0x01100000      /* as per CCSR map. */
@@ -128,6 +120,8 @@
 #define DCFG_PORSR1_RCW_SRC_NOR                0x12f00000
 #define DCFG_RCWSR13                   0x130
 #define DCFG_RCWSR13_DSPI              (0 << 8)
+#define DCFG_RCWSR15                   0x138
+#define DCFG_RCWSR15_IFCGRPABASE_QSPI  0x3
 
 #define DCFG_DCSR_BASE         0X700100000ULL
 #define DCFG_DCSR_PORCR1               0x000
@@ -140,6 +134,7 @@
 #define SCFG_BASE              0x01fc0000
 #define SCFG_USB3PRM1CR                        0x000
 #define SCFG_USB3PRM1CR_INIT           0x27672b2a
+#define SCFG_QSPICLKCTLR       0x10
 
 #define TP_ITYP_AV             0x00000001      /* Initiator available */
 #define TP_ITYP_TYPE(x)        (((x) & 0x6) >> 1)      /* Initiator Type */
@@ -152,6 +147,7 @@
 #define TY_ITYP_VER_A7         0x1
 #define TY_ITYP_VER_A53                0x2
 #define TY_ITYP_VER_A57                0x3
+#define TY_ITYP_VER_A72                0x4
 
 #define TP_CLUSTER_EOC         0x80000000      /* end of clusters */
 #define TP_CLUSTER_INIT_MASK   0x0000003f      /* initiator mask */