Merge branch 'master' of git://git.denx.de/u-boot

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch3.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
index 081519aef7ef3982a31dbe3ad004f6f1e9da2fe6..65b3357009a5deac414d80b4774aab750784dc68 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h
@@ -73,6 +73,36 @@
 #define AHCI_BASE_ADDR1                                (CONFIG_SYS_IMMR + 0x02200000)
 #define AHCI_BASE_ADDR2                                (CONFIG_SYS_IMMR + 0x02210000)
 
+/* SFP */
+#define CONFIG_SYS_SFP_ADDR            (CONFIG_SYS_IMMR + 0x00e80200)
+
+/* SEC */
+#define CONFIG_SYS_FSL_SEC_OFFSET              0x07000000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET              0x07010000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
+/* Security Monitor */
+#define CONFIG_SYS_SEC_MON_ADDR                (CONFIG_SYS_IMMR + 0x00e90000)
+
+/* MMU 500 */
+#define SMMU_SCR0                      (SMMU_BASE + 0x0)
+#define SMMU_SCR1                      (SMMU_BASE + 0x4)
+#define SMMU_SCR2                      (SMMU_BASE + 0x8)
+#define SMMU_SACR                      (SMMU_BASE + 0x10)
+#define SMMU_IDR0                      (SMMU_BASE + 0x20)
+#define SMMU_IDR1                      (SMMU_BASE + 0x24)
+
+#define SMMU_NSCR0                     (SMMU_BASE + 0x400)
+#define SMMU_NSCR2                     (SMMU_BASE + 0x408)
+#define SMMU_NSACR                     (SMMU_BASE + 0x410)
+
+#define SCR0_CLIENTPD_MASK             0x00000001
+#define SCR0_USFCFG_MASK               0x00000400
+
+
 /* PCIe */
 #define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
@@ -154,6 +184,10 @@ struct ccsr_gur {
        u8      res_008[0x20-0x8];
        u32     gpporcr1;       /* General-purpose POR configuration */
        u32     gpporcr2;       /* General-purpose POR configuration 2 */
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_SHIFT     25
+#define FSL_CHASSIS3_DCFG_FUSESR_VID_MASK      0x1F
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_SHIFT  20
+#define FSL_CHASSIS3_DCFG_FUSESR_ALTVID_MASK   0x1F
        u32     dcfg_fusesr;    /* Fuse status register */
        u32     gpporcr3;
        u32     gpporcr4;
@@ -209,6 +243,8 @@ struct ccsr_gur {
 #define        FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT  16
 #define        FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK   0xFF000000
 #define        FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT  24
+#define RCW_SB_EN_REG_INDEX    9
+#define RCW_SB_EN_MASK         0x00000400
 
        u8      res_180[0x200-0x180];
        u32     scratchrw[32];  /* Scratch Read/Write */