armv8: fsl-lsch3: Update VID support

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch2.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 0bad0c70b847e1a68fab55d1a1c52cc5634a710c..8ad199f60a1d1d67e68aef8ae160cc4989dcb3ed 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
 #define CONFIG_SYS_GIC400_ADDR                 (CONFIG_SYS_IMMR + 0x00400000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)
+#define SYS_FSL_QSPI_ADDR                      (CONFIG_SYS_IMMR + 0x00550000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_CSU_ADDR                        (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_FSL_GUTS_ADDR               (CONFIG_SYS_IMMR + 0x00ee0000)
@@ -31,14 +32,12 @@
 #define CONFIG_SYS_NS16550_COM2                        (CONFIG_SYS_IMMR + 0x011c0600)
 #define CONFIG_SYS_NS16550_COM3                        (CONFIG_SYS_IMMR + 0x011d0500)
 #define CONFIG_SYS_NS16550_COM4                        (CONFIG_SYS_IMMR + 0x011d0600)
-#define CONFIG_SYS_LS1043A_XHCI_USB1_ADDR      (CONFIG_SYS_IMMR + 0x01f00000)
-#define CONFIG_SYS_LS1043A_XHCI_USB2_ADDR      (CONFIG_SYS_IMMR + 0x02000000)
-#define CONFIG_SYS_LS1043A_XHCI_USB3_ADDR      (CONFIG_SYS_IMMR + 0x02100000)
+#define CONFIG_SYS_XHCI_USB1_ADDR              (CONFIG_SYS_IMMR + 0x01f00000)
+#define CONFIG_SYS_XHCI_USB2_ADDR              (CONFIG_SYS_IMMR + 0x02000000)
+#define CONFIG_SYS_XHCI_USB3_ADDR              (CONFIG_SYS_IMMR + 0x02100000)
 #define CONFIG_SYS_PCIE1_ADDR                  (CONFIG_SYS_IMMR + 0x2400000)
 #define CONFIG_SYS_PCIE2_ADDR                  (CONFIG_SYS_IMMR + 0x2500000)
 #define CONFIG_SYS_PCIE3_ADDR                  (CONFIG_SYS_IMMR + 0x2600000)
-#define CONFIG_SYS_FSL_SEC_ADDR                        (CONFIG_SYS_IMMR + 0x700000)
-#define CONFIG_SYS_FSL_JR0_ADDR                        (CONFIG_SYS_IMMR + 0x710000)
 #define CONFIG_SYS_SEC_MON_ADDR                        (CONFIG_SYS_IMMR + 0xe90000)
 #define CONFIG_SYS_SFP_ADDR                    (CONFIG_SYS_IMMR + 0xe80200)
 
@@ -62,7 +61,11 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR             0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR             0x5000000000ULL
 /* LUT registers */
+#ifdef CONFIG_ARCH_LS1012A
+#define PCIE_LUT_BASE                          0xC0000
+#else
 #define PCIE_LUT_BASE                          0x10000
+#endif
 #define PCIE_LUT_LCTRL0                                0x7F8
 #define PCIE_LUT_DBG                           0x7FC
 
@@ -92,6 +95,7 @@
 #define TY_ITYP_VER_A7          0x1
 #define TY_ITYP_VER_A53         0x2
 #define TY_ITYP_VER_A57         0x3
+#define TY_ITYP_VER_A72                0x4
 
 #define TP_CLUSTER_EOC         0xc0000000      /* end of clusters */
 #define TP_CLUSTER_INIT_MASK    0x0000003f      /* initiator mask */
@@ -117,7 +121,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR             CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR             0x01000000
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
@@ -125,7 +129,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW    0x01000000
 #endif
 
 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
@@ -133,6 +137,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 
 struct sys_info {
        unsigned long freq_processor[CONFIG_MAX_CPUS];
+       /* frequency of platform PLL */
        unsigned long freq_systembus;
        unsigned long freq_ddrbus;
        unsigned long freq_localbus;
@@ -157,7 +162,16 @@ struct sys_info {
 #define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR         \
                (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET)
 
+#define CONFIG_SYS_FSL_SEC_OFFSET              0x700000ull
+#define CONFIG_SYS_FSL_JR0_OFFSET              0x710000ull
+#define CONFIG_SYS_FSL_SEC_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET)
+#define CONFIG_SYS_FSL_JR0_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
+
 /* Device Configuration and Pin Control */
+#define DCFG_DCSR_PORCR1               0x0
+
 struct ccsr_gur {
        u32     porsr1;         /* POR status 1 */
 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK      0xFF800000
@@ -218,6 +232,8 @@ struct ccsr_gur {
 #define FSL_CHASSIS2_RCWSR0_MEM_PLL_RAT_MASK   0x3f
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK   0xffff0000
 #define FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT  16
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK   0x0000ffff
+#define FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT  0
 #define RCW_SB_EN_REG_INDEX    7
 #define RCW_SB_EN_MASK         0x00200000
 
@@ -323,6 +339,8 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP                0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP                0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP       0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP       0x00400000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {
@@ -343,7 +361,8 @@ struct ccsr_scfg {
        u32 qspi_cfg;
        u8 res_160[0x180-0x160];
        u32 dmamcr;
-       u8 res_184[0x18c-0x184];
+       u8 res_184[0x188-0x184];
+       u32 gic_align;
        u32 debug_icid;
        u8 res_190[0x1a4-0x190];
        u32 snpcnfgcr;
@@ -587,4 +606,6 @@ struct ccsr_cci400 {
 #define SCR0_CLIENTPD_MASK             0x00000001
 #define SCR0_USFCFG_MASK               0x00000400
 
+uint get_svr(void);
+
 #endif /* __ARCH_FSL_LSCH2_IMMAP_H__*/