armv8/fsl-lsch2: refactor the clock system initialization

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / immap_lsch2.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index df5187195df32bb19f5bb72a1e56b904db76d37a..6ace3daf01cd95459c60d8aa37f4120bdfb0184d 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -18,6 +18,7 @@
 #define CONFIG_SYS_CCI400_ADDR                 (CONFIG_SYS_IMMR + 0x00180000)
 #define CONFIG_SYS_GIC400_ADDR                 (CONFIG_SYS_IMMR + 0x00400000)
 #define CONFIG_SYS_IFC_ADDR                    (CONFIG_SYS_IMMR + 0x00530000)
+#define SYS_FSL_QSPI_ADDR                      (CONFIG_SYS_IMMR + 0x00550000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR              (CONFIG_SYS_IMMR + 0x00560000)
 #define CONFIG_SYS_FSL_CSU_ADDR                        (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_FSL_GUTS_ADDR               (CONFIG_SYS_IMMR + 0x00ee0000)
@@ -120,7 +121,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR
-#define CONFIG_SYS_CCSRBAR             CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR             0x01000000
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR_PHYS_HIGH
@@ -128,7 +129,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 #endif
 
 #ifndef CONFIG_SYS_CCSRBAR_PHYS_LOW
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW    CONFIG_SYS_CCSRBAR_DEFAULT
+#define CONFIG_SYS_CCSRBAR_PHYS_LOW    0x01000000
 #endif
 
 #define CONFIG_SYS_CCSRBAR_PHYS ((CONFIG_SYS_CCSRBAR_PHYS_HIGH * 1ull) << 32 | \
@@ -136,6 +137,7 @@ CONFIG_SYS_CCSRBAR_PHYS_LOW and/or CONFIG_SYS_CCSRBAR_PHYS_HIGH instead."
 
 struct sys_info {
        unsigned long freq_processor[CONFIG_MAX_CPUS];
+       /* frequency of platform PLL */
        unsigned long freq_systembus;
        unsigned long freq_ddrbus;
        unsigned long freq_localbus;
@@ -168,6 +170,8 @@ struct sys_info {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET)
 
 /* Device Configuration and Pin Control */
+#define DCFG_DCSR_PORCR1               0x0
+
 struct ccsr_gur {
        u32     porsr1;         /* POR status 1 */
 #define FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK      0xFF800000
@@ -335,6 +339,8 @@ struct ccsr_gur {
 
 #define SCFG_SNPCNFGCR_SECRDSNP                0x80000000
 #define SCFG_SNPCNFGCR_SECWRSNP                0x40000000
+#define SCFG_SNPCNFGCR_SATARDSNP       0x00800000
+#define SCFG_SNPCNFGCR_SATAWRSNP       0x00400000
 
 /* Supplemental Configuration Unit */
 struct ccsr_scfg {