Merge branch 'master' of git://git.denx.de/u-boot

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / cpu.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index f75faa6ffe3217a1229206dbd5f2c5031c610426..1cebe2fbb010736ae0e35a944773a025e3638701 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -14,6 +14,7 @@ static struct cpu_type cpu_type_list[] = {
        CPU_TYPE_ENTRY(LS1043, LS1043, 4),
        CPU_TYPE_ENTRY(LS1023, LS1023, 2),
        CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+       CPU_TYPE_ENTRY(LS1012, LS1012, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF
@@ -157,9 +158,11 @@ static const struct sys_mmu_table early_mmu_table[] = {
        { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
          CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 #endif
 };
 
@@ -204,7 +207,7 @@ static const struct sys_mmu_table final_mmu_table[] = {
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
          CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
-#if defined(CONFIG_LS2080A) || defined(CONFIG_LS2085A)
+#ifdef CONFIG_LS2080A
        { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
          CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
@@ -245,7 +248,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
          CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
        { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
          CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
@@ -256,7 +260,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
          CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
-         CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL, PTE_BLOCK_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 #endif
 };
 #endif