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sunxi: Use BROM stored boot_media value to determine our boot-source
[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / cpu.h
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index b7b8e5dcd97077b1b85e50bc36ba1bac7f36d2eb..197b0eb5a53a4a3ed8724b61ab2f41ec05305e62 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -8,9 +8,13 @@
 #define _FSL_LAYERSCAPE_CPU_H
 
 static struct cpu_type cpu_type_list[] = {
-       CPU_TYPE_ENTRY(LS2085, LS2085, 8),
-       CPU_TYPE_ENTRY(LS2080, LS2080, 8),
-       CPU_TYPE_ENTRY(LS2045, LS2045, 4),
+       CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+       CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+       CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+       CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+       CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+       CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+       CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF
@@ -73,6 +77,28 @@ static struct cpu_type cpu_type_list[] = {
 #define CONFIG_SYS_FSL_PEBUF_SIZE      0x400000000
 #define CONFIG_SYS_FSL_DRAM_BASE2      0x8080000000
 #define CONFIG_SYS_FSL_DRAM_SIZE2      0x7F80000000
+#elif defined(CONFIG_FSL_LSCH2)
+#define CONFIG_SYS_FSL_BOOTROM_BASE    0x0
+#define CONFIG_SYS_FSL_BOOTROM_SIZE    0x1000000
+#define CONFIG_SYS_FSL_CCSR_BASE       0x1000000
+#define CONFIG_SYS_FSL_CCSR_SIZE       0xf000000
+#define CONFIG_SYS_FSL_DCSR_BASE       0x20000000
+#define CONFIG_SYS_FSL_DCSR_SIZE       0x4000000
+#define CONFIG_SYS_FSL_QSPI_BASE       0x40000000
+#define CONFIG_SYS_FSL_QSPI_SIZE       0x20000000
+#define CONFIG_SYS_FSL_IFC_BASE                0x60000000
+#define CONFIG_SYS_FSL_IFC_SIZE                0x20000000
+#define CONFIG_SYS_FSL_DRAM_BASE1      0x80000000
+#define CONFIG_SYS_FSL_DRAM_SIZE1      0x80000000
+#define CONFIG_SYS_FSL_QBMAN_BASE      0x500000000
+#define CONFIG_SYS_FSL_QBMAN_SIZE      0x10000000
+#define CONFIG_SYS_FSL_DRAM_BASE2      0x880000000
+#define CONFIG_SYS_FSL_DRAM_SIZE2      0x780000000     /* 30GB */
+#define CONFIG_SYS_PCIE1_PHYS_SIZE     0x800000000
+#define CONFIG_SYS_PCIE2_PHYS_SIZE     0x800000000
+#define CONFIG_SYS_PCIE3_PHYS_SIZE     0x800000000
+#define CONFIG_SYS_FSL_DRAM_BASE3      0x8800000000
+#define CONFIG_SYS_FSL_DRAM_SIZE3      0x7800000000    /* 480GB */
 #endif
 
 struct sys_mmu_table {
@@ -80,7 +106,7 @@ struct sys_mmu_table {
        u64 phys_addr;
        u64 size;
        u64 memory_type;
-       u64 share;
+       u64 attribute;
 };
 
 struct table_info {
@@ -92,70 +118,154 @@ struct table_info {
 static const struct sys_mmu_table early_mmu_table[] = {
 #ifdef CONFIG_FSL_LSCH3
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
        /* For IFC Region #1, only the first 4MB is cache-enabled */
        { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
-         CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
          CONFIG_SYS_FSL_IFC_BASE1 + CONFIG_SYS_FSL_IFC_SIZE1_1,
          CONFIG_SYS_FSL_IFC_SIZE1 - CONFIG_SYS_FSL_IFC_SIZE1_1,
-         MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FSL_IFC_BASE1,
-         CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_IFC_SIZE1, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+       /* Map IFC region #2 up to CONFIG_SYS_FLASH_BASE for NAND boot */
+       { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
+         CONFIG_SYS_FLASH_BASE - CONFIG_SYS_FSL_IFC_BASE2,
+         MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+#elif defined(CONFIG_FSL_LSCH2)
+       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+         CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+         CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 #endif
 };
 
 static const struct sys_mmu_table final_mmu_table[] = {
 #ifdef CONFIG_FSL_LSCH3
        { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
-         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
-         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
-         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
        { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
-         CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_IFC_BASE2, CONFIG_SYS_FSL_IFC_BASE2,
-         CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_IFC_SIZE2, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
        { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
-         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_MC_BASE, CONFIG_SYS_FSL_MC_BASE,
-         CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_MC_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_NI_BASE, CONFIG_SYS_FSL_NI_BASE,
-         CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_NI_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        /* For QBMAN portal, only the first 64MB is cache-enabled */
        { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
-         CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_QBMAN_SIZE_1, MT_NORMAL,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN | PTE_BLOCK_NS },
        { CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
          CONFIG_SYS_FSL_QBMAN_BASE + CONFIG_SYS_FSL_QBMAN_SIZE_1,
          CONFIG_SYS_FSL_QBMAN_SIZE - CONFIG_SYS_FSL_QBMAN_SIZE_1,
-         MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
-         CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
-         CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
-         CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
-#ifdef CONFIG_LS2085A
+         CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+#ifdef CONFIG_LS2080A
        { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR,
-         CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_PCIE4_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
 #endif
        { CONFIG_SYS_FSL_WRIOP1_BASE, CONFIG_SYS_FSL_WRIOP1_BASE,
-         CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_WRIOP1_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_AIOP1_BASE, CONFIG_SYS_FSL_AIOP1_BASE,
-         CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_AIOP1_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_PEBUF_BASE, CONFIG_SYS_FSL_PEBUF_BASE,
-         CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE },
+         CONFIG_SYS_FSL_PEBUF_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
-         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL, PMD_SECT_OUTER_SHARE },
+         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+#elif defined(CONFIG_FSL_LSCH2)
+       { CONFIG_SYS_FSL_BOOTROM_BASE, CONFIG_SYS_FSL_BOOTROM_BASE,
+         CONFIG_SYS_FSL_BOOTROM_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_FSL_CCSR_BASE, CONFIG_SYS_FSL_CCSR_BASE,
+         CONFIG_SYS_FSL_CCSR_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
+         CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_DCSR_BASE, CONFIG_SYS_FSL_DCSR_BASE,
+         CONFIG_SYS_FSL_DCSR_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE,
+         CONFIG_SYS_FSL_QSPI_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_FSL_IFC_BASE, CONFIG_SYS_FSL_IFC_BASE,
+         CONFIG_SYS_FSL_IFC_SIZE, MT_DEVICE_NGNRNE, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
+         CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+       { CONFIG_SYS_FSL_QBMAN_BASE, CONFIG_SYS_FSL_QBMAN_BASE,
+         CONFIG_SYS_FSL_QBMAN_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_FSL_DRAM_BASE2, CONFIG_SYS_FSL_DRAM_BASE2,
+         CONFIG_SYS_FSL_DRAM_SIZE2, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+       { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR,
+         CONFIG_SYS_PCIE1_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR,
+         CONFIG_SYS_PCIE2_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR,
+         CONFIG_SYS_PCIE3_PHYS_SIZE, MT_DEVICE_NGNRNE,
+         PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
+       { CONFIG_SYS_FSL_DRAM_BASE3, CONFIG_SYS_FSL_DRAM_BASE3,
+         CONFIG_SYS_FSL_DRAM_SIZE3, MT_NORMAL,
+         PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
 #endif
 };
 #endif
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