sunxi: Use BROM stored boot_media value to determine our boot-source

[oweals/u-boot.git] / arch / arm / include / asm / arch-fsl-layerscape / cpu.h

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
index 702b9faabd9f23e11918008c929f80e821e3a884..197b0eb5a53a4a3ed8724b61ab2f41ec05305e62 100644 (file)
--- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h
@@ -8,12 +8,13 @@
 #define _FSL_LAYERSCAPE_CPU_H
 
 static struct cpu_type cpu_type_list[] = {
-       CPU_TYPE_ENTRY(LS2080, LS2080, 8),
-       CPU_TYPE_ENTRY(LS2085, LS2085, 8),
-       CPU_TYPE_ENTRY(LS2045, LS2045, 4),
-       CPU_TYPE_ENTRY(LS1043, LS1043, 4),
-       CPU_TYPE_ENTRY(LS1023, LS1023, 2),
-       CPU_TYPE_ENTRY(LS2040, LS2040, 4),
+       CPU_TYPE_ENTRY(LS2080A, LS2080A, 8),
+       CPU_TYPE_ENTRY(LS2085A, LS2085A, 8),
+       CPU_TYPE_ENTRY(LS2045A, LS2045A, 4),
+       CPU_TYPE_ENTRY(LS1043A, LS1043A, 4),
+       CPU_TYPE_ENTRY(LS1023A, LS1023A, 2),
+       CPU_TYPE_ENTRY(LS2040A, LS2040A, 4),
+       CPU_TYPE_ENTRY(LS1012A, LS1012A, 1),
 };
 
 #ifndef CONFIG_SYS_DCACHE_OFF
@@ -121,6 +122,8 @@ static const struct sys_mmu_table early_mmu_table[] = {
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },
        { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE,
          CONFIG_SYS_FSL_OCRAM_SIZE, MT_NORMAL, PTE_BLOCK_NON_SHARE },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
        /* For IFC Region #1, only the first 4MB is cache-enabled */
        { CONFIG_SYS_FSL_IFC_BASE1, CONFIG_SYS_FSL_IFC_BASE1,
          CONFIG_SYS_FSL_IFC_SIZE1_1, MT_NORMAL, PTE_BLOCK_NON_SHARE },
@@ -175,6 +178,8 @@ static const struct sys_mmu_table final_mmu_table[] = {
        { CONFIG_SYS_FSL_DRAM_BASE1, CONFIG_SYS_FSL_DRAM_BASE1,
          CONFIG_SYS_FSL_DRAM_SIZE1, MT_NORMAL,
          PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS },
+       { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1,
+         CONFIG_SYS_FSL_QSPI_SIZE1,  MT_NORMAL, PTE_BLOCK_NON_SHARE},
        { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2,
          CONFIG_SYS_FSL_QSPI_SIZE2, MT_DEVICE_NGNRNE,
          PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN },