Merge branch 'dcc' of git://www.denx.de/git/u-boot-microblaze

[oweals/u-boot.git] / arch / arm / include / asm / arch-davinci / pll_defs.h

diff --git a/arch/arm/include/asm/arch-davinci/pll_defs.h b/arch/arm/include/asm/arch-davinci/pll_defs.h
index 5d3761637df968926f53f3371318e2b83eb21ee8..d083cccadb3dd8fc9f76452dbf783683fdeb1403 100644 (file)
--- a/arch/arm/include/asm/arch-davinci/pll_defs.h
+++ b/arch/arm/include/asm/arch-davinci/pll_defs.h
@@ -2,23 +2,7 @@
  * Copyright (C) 2011
  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 #ifndef _DV_PLL_DEFS_H_
 #define _DV_PLL_DEFS_H_
@@ -57,11 +41,25 @@ struct dv_pll_regs {
        unsigned int    plldiv9;        /* 0x174 */
 };
 
+#define PLL_MASTER_LOCK        (1 << 4)
+
+#define PLLCTL_CLOCK_MODE_SHIFT        8
 #define PLLCTL_PLLEN   (1 << 0)
 #define PLLCTL_PLLPWRDN        (1 << 1)
 #define PLLCTL_PLLRST  (1 << 3)
+#define PLLCTL_PLLDIS  (1 << 4)
 #define PLLCTL_PLLENSRC        (1 << 5)
 #define PLLCTL_RES_9   (1 << 8)
+#define PLLCTL_EXTCLKSRC       (1 << 9)
+
+#define PLL_DIVEN      (1 << 15)
+#define PLL_POSTDEN    PLL_DIVEN
+
+#define PLL_SCSCFG3_DIV45PENA  (1 << 2)
+#define PLL_SCSCFG3_EMA_CLKSRC (1 << 1)
+
+#define PLL_RSTYPE_POR         (1 << 0)
+#define PLL_RSTYPE_XWRST       (1 << 1)
 
 #define PLLSECCTL_TINITZ       (1 << 16)
 #define PLLSECCTL_TENABLE      (1 << 17)
@@ -69,6 +67,7 @@ struct dv_pll_regs {
 #define PLLSECCTL_STOPMODE     (1 << 22)
 
 #define PLLCMD_GOSET           (1 << 0)
+#define PLLCMD_GOSTAT          (1 << 0)
 
 #define PLL0_LOCK              0x07000000
 #define PLL1_LOCK              0x07000000
@@ -76,4 +75,9 @@ struct dv_pll_regs {
 #define dv_pll0_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL0_BASE)
 #define dv_pll1_regs ((struct dv_pll_regs *)DAVINCI_PLL_CNTRL1_BASE)
 
+#define ARM_PLLDIV     (offsetof(struct dv_pll_regs, plldiv2))
+#define DDR_PLLDIV     (offsetof(struct dv_pll_regs, plldiv7))
+#define SPI_PLLDIV     (offsetof(struct dv_pll_regs, plldiv4))
+
+unsigned int davinci_clk_get(unsigned int div);
 #endif /* _DV_PLL_DEFS_H_ */