/* VTP Base address */
#define VTP0_CTRL_ADDR 0x48140E0C
+#define VTP1_CTRL_ADDR 0x48140E10
/* DDR Base address */
#define DDR_PHY_CMD_ADDR 0x47C0C400
#define DDR_PHY_DATA_ADDR 0x47C0C4C8
+#define DDR_PHY_CMD_ADDR2 0x47C0C800
+#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
#define DDR_DATA_REGS_NR 4
+#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
+#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
+
/* CPSW Config space */
#define CPSW_MDIO_BASE 0x4A100800