pcm051: Add support for Phytec phyCORE-AM335x
[oweals/u-boot.git] / arch / arm / include / asm / arch-am33xx / ddr_defs.h
index 8e69fb67b14bf53b85b263a551862c3cf434507a..f95b332133ebf540b8a9c9e54521b63a599d15b5 100644 (file)
 #define MT41J128MJT125_PHY_FIFO_WE             0x100
 #define MT41J128MJT125_IOCTRL_VALUE            0x18B
 
+/* Micron MT41J256M8HX-15E */
+#define MT41J256M8HX15E_EMIF_READ_LATENCY      0x06
+#define MT41J256M8HX15E_EMIF_TIM1              0x0888A39B
+#define MT41J256M8HX15E_EMIF_TIM2              0x26337FDA
+#define MT41J256M8HX15E_EMIF_TIM3              0x501F830F
+#define MT41J256M8HX15E_EMIF_SDCFG             0x61C04B32
+#define MT41J256M8HX15E_EMIF_SDREF             0x0000093B
+#define MT41J256M8HX15E_ZQ_CFG                 0x50074BE4
+#define MT41J256M8HX15E_DLL_LOCK_DIFF          0x1
+#define MT41J256M8HX15E_RATIO                  0x40
+#define MT41J256M8HX15E_INVERT_CLKOUT          0x1
+#define MT41J256M8HX15E_RD_DQS                 0x3B
+#define MT41J256M8HX15E_WR_DQS                 0x85
+#define MT41J256M8HX15E_PHY_WR_DATA            0xC1
+#define MT41J256M8HX15E_PHY_FIFO_WE            0x100
+#define MT41J256M8HX15E_IOCTRL_VALUE           0x18B
+
+
 /**
  * Configure SDRAM
  */