Merge branch 'master' of git://git.denx.de/u-boot-mips

[oweals/u-boot.git] / arch / arm / include / asm / arch-am33xx / ddr_defs.h

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 6b22c45f77525380883835ec5a151424e6ad9db3..8e69fb67b14bf53b85b263a551862c3cf434507a 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -29,40 +29,41 @@
 #define PHY_DLL_LOCK_DIFF      0x0
 #define DDR_CKE_CTRL_NORMAL    0x1
 
-#define DDR2_EMIF_READ_LATENCY 0x100005        /* Enable Dynamic Power Down */
-#define DDR2_EMIF_TIM1         0x0666B3C9
-#define DDR2_EMIF_TIM2         0x243631CA
-#define DDR2_EMIF_TIM3         0x0000033F
-#define DDR2_EMIF_SDCFG                0x41805332
-#define DDR2_EMIF_SDREF                0x0000081a
-#define DDR2_DLL_LOCK_DIFF     0x0
-#define DDR2_RATIO             0x80
-#define DDR2_INVERT_CLKOUT     0x00
-#define DDR2_RD_DQS            0x12
-#define DDR2_WR_DQS            0x00
-#define DDR2_PHY_WRLVL         0x00
-#define DDR2_PHY_GATELVL       0x00
-#define DDR2_PHY_WR_DATA       0x40
-#define DDR2_PHY_FIFO_WE       0x80
-#define DDR2_PHY_RANK0_DELAY   0x1
-#define DDR2_IOCTRL_VALUE      0x18B
+/* Micron MT47H128M16RT-25E */
+#define MT47H128M16RT25E_EMIF_READ_LATENCY     0x100005
+#define MT47H128M16RT25E_EMIF_TIM1             0x0666B3C9
+#define MT47H128M16RT25E_EMIF_TIM2             0x243631CA
+#define MT47H128M16RT25E_EMIF_TIM3             0x0000033F
+#define MT47H128M16RT25E_EMIF_SDCFG            0x41805332
+#define MT47H128M16RT25E_EMIF_SDREF            0x0000081a
+#define MT47H128M16RT25E_DLL_LOCK_DIFF         0x0
+#define MT47H128M16RT25E_RATIO                 0x80
+#define MT47H128M16RT25E_INVERT_CLKOUT         0x00
+#define MT47H128M16RT25E_RD_DQS                        0x12
+#define MT47H128M16RT25E_WR_DQS                        0x00
+#define MT47H128M16RT25E_PHY_WRLVL             0x00
+#define MT47H128M16RT25E_PHY_GATELVL           0x00
+#define MT47H128M16RT25E_PHY_WR_DATA           0x40
+#define MT47H128M16RT25E_PHY_FIFO_WE           0x80
+#define MT47H128M16RT25E_PHY_RANK0_DELAY               0x1
+#define MT47H128M16RT25E_IOCTRL_VALUE          0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define DDR3_EMIF_READ_LATENCY 0x06
-#define DDR3_EMIF_TIM1         0x0888A39B
-#define DDR3_EMIF_TIM2         0x26337FDA
-#define DDR3_EMIF_TIM3         0x501F830F
-#define DDR3_EMIF_SDCFG                0x61C04AB2
-#define DDR3_EMIF_SDREF                0x0000093B
-#define DDR3_ZQ_CFG            0x50074BE4
-#define DDR3_DLL_LOCK_DIFF     0x1
-#define DDR3_RATIO             0x40
-#define DDR3_INVERT_CLKOUT     0x1
-#define DDR3_RD_DQS            0x3B
-#define DDR3_WR_DQS            0x85
-#define DDR3_PHY_WR_DATA       0xC1
-#define DDR3_PHY_FIFO_WE       0x100
-#define DDR3_IOCTRL_VALUE      0x18B
+#define MT41J128MJT125_EMIF_READ_LATENCY       0x06
+#define MT41J128MJT125_EMIF_TIM1               0x0888A39B
+#define MT41J128MJT125_EMIF_TIM2               0x26337FDA
+#define MT41J128MJT125_EMIF_TIM3               0x501F830F
+#define MT41J128MJT125_EMIF_SDCFG              0x61C04AB2
+#define MT41J128MJT125_EMIF_SDREF              0x0000093B
+#define MT41J128MJT125_ZQ_CFG                  0x50074BE4
+#define MT41J128MJT125_DLL_LOCK_DIFF           0x1
+#define MT41J128MJT125_RATIO                   0x40
+#define MT41J128MJT125_INVERT_CLKOUT           0x1
+#define MT41J128MJT125_RD_DQS                  0x3B
+#define MT41J128MJT125_WR_DQS                  0x85
+#define MT41J128MJT125_PHY_WR_DATA             0xC1
+#define MT41J128MJT125_PHY_FIFO_WE             0x100
+#define MT41J128MJT125_IOCTRL_VALUE            0x18B
 
 /**
  * Configure SDRAM
@@ -189,6 +190,8 @@ struct ddr_ctrl {
        unsigned int ddrckectrl;
 };
 
-void config_ddr(short ddr_type);
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+               const struct ddr_data *data, const struct cmd_control *ctrl,
+               const struct emif_regs *regs);
 
 #endif  /* _DDR_DEFS_H */