ARM: tegra: pinctrl: remove vddio

[oweals/u-boot.git] / arch / arm / include / asm / arch-am33xx / ddr_defs.h

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 6af4b84e568bca75c8e3c5dee6fb8a524c08ada4..4d899528f5bc157fc0affd398670c4e33dce969b 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -43,7 +43,7 @@
 #define MT47H128M16RT25E_IOCTRL_VALUE          0x18B
 
 /* Micron MT41J128M16JT-125 */
-#define MT41J128MJT125_EMIF_READ_LATENCY       0x06
+#define MT41J128MJT125_EMIF_READ_LATENCY       0x100006
 #define MT41J128MJT125_EMIF_TIM1               0x0888A39B
 #define MT41J128MJT125_EMIF_TIM2               0x26337FDA
 #define MT41J128MJT125_EMIF_TIM3               0x501F830F
@@ -58,6 +58,22 @@
 #define MT41J128MJT125_PHY_FIFO_WE             0x100
 #define MT41J128MJT125_IOCTRL_VALUE            0x18B
 
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY      0x06
+#define MT41K128MJT187E_EMIF_TIM1              0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2              0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3              0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG             0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF             0x0000093B
+#define MT41K128MJT187E_ZQ_CFG                 0x50074BE4
+#define MT41K128MJT187E_RATIO                  0x40
+#define MT41K128MJT187E_INVERT_CLKOUT          0x1
+#define MT41K128MJT187E_RD_DQS                 0x3B
+#define MT41K128MJT187E_WR_DQS                 0x85
+#define MT41K128MJT187E_PHY_WR_DATA            0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE            0x100
+#define MT41K128MJT187E_IOCTRL_VALUE           0x18B
+
 /* Micron MT41J64M16JT-125 */
 #define MT41J64MJT125_EMIF_SDCFG               0x61C04A32
 
@@ -65,7 +81,7 @@
 #define MT41J256MJT125_EMIF_SDCFG              0x61C04B32
 
 /* Micron MT41J256M8HX-15E */
-#define MT41J256M8HX15E_EMIF_READ_LATENCY      0x06
+#define MT41J256M8HX15E_EMIF_READ_LATENCY      0x100006
 #define MT41J256M8HX15E_EMIF_TIM1              0x0888A39B
 #define MT41J256M8HX15E_EMIF_TIM2              0x26337FDA
 #define MT41J256M8HX15E_EMIF_TIM3              0x501F830F
@@ -97,7 +113,7 @@
 #define MT41K256M16HA125E_IOCTRL_VALUE         0x18B
 
 /* Micron MT41J512M8RH-125 on EVM v1.5 */
-#define MT41J512M8RH125_EMIF_READ_LATENCY      0x06
+#define MT41J512M8RH125_EMIF_READ_LATENCY      0x100006
 #define MT41J512M8RH125_EMIF_TIM1              0x0888A39B
 #define MT41J512M8RH125_EMIF_TIM2              0x26517FDA
 #define MT41J512M8RH125_EMIF_TIM3              0x501F84EF
@@ -113,7 +129,7 @@
 #define MT41J512M8RH125_IOCTRL_VALUE           0x18B
 
 /* Samsung K4B2G1646E-BIH9 */
-#define K4B2G1646EBIH9_EMIF_READ_LATENCY       0x07
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY       0x100007
 #define K4B2G1646EBIH9_EMIF_TIM1               0x0AAAE51B
 #define K4B2G1646EBIH9_EMIF_TIM2               0x2A1D7FDA
 #define K4B2G1646EBIH9_EMIF_TIM3               0x501F83FF
@@ -136,6 +152,14 @@
 #define  LPDDR2_DATA2_IOCTRL_VALUE   0x20000294
 #define  LPDDR2_DATA3_IOCTRL_VALUE   0x20000294
 
+#define  DDR3_ADDRCTRL_WD0_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_WD1_IOCTRL_VALUE 0x00000000
+#define  DDR3_ADDRCTRL_IOCTRL_VALUE   0x84
+#define  DDR3_DATA0_IOCTRL_VALUE   0x84
+#define  DDR3_DATA1_IOCTRL_VALUE   0x84
+#define  DDR3_DATA2_IOCTRL_VALUE   0x84
+#define  DDR3_DATA3_IOCTRL_VALUE   0x84
+
 /**
  * Configure DMM
  */