#define MT47H128M16RT25E_EMIF_SDCFG 0x41805332
#define MT47H128M16RT25E_EMIF_SDREF 0x0000081a
#define MT47H128M16RT25E_RATIO 0x80
-#define MT47H128M16RT25E_INVERT_CLKOUT 0x00
#define MT47H128M16RT25E_RD_DQS 0x12
-#define MT47H128M16RT25E_WR_DQS 0x00
-#define MT47H128M16RT25E_PHY_WRLVL 0x00
-#define MT47H128M16RT25E_PHY_GATELVL 0x00
#define MT47H128M16RT25E_PHY_WR_DATA 0x40
#define MT47H128M16RT25E_PHY_FIFO_WE 0x80
#define MT47H128M16RT25E_IOCTRL_VALUE 0x18B
/* Micron MT41J128M16JT-125 */
-#define MT41J128MJT125_EMIF_READ_LATENCY 0x06
+#define MT41J128MJT125_EMIF_READ_LATENCY 0x100006
#define MT41J128MJT125_EMIF_TIM1 0x0888A39B
#define MT41J128MJT125_EMIF_TIM2 0x26337FDA
#define MT41J128MJT125_EMIF_TIM3 0x501F830F
#define MT41J128MJT125_PHY_FIFO_WE 0x100
#define MT41J128MJT125_IOCTRL_VALUE 0x18B
+/* Micron MT41J128M16JT-125 at 400MHz*/
+#define MT41J128MJT125_EMIF_READ_LATENCY_400MHz 0x100007
+#define MT41J128MJT125_EMIF_TIM1_400MHz 0x0AAAD4DB
+#define MT41J128MJT125_EMIF_TIM2_400MHz 0x26437FDA
+#define MT41J128MJT125_EMIF_TIM3_400MHz 0x501F83FF
+#define MT41J128MJT125_EMIF_SDCFG_400MHz 0x61C052B2
+#define MT41J128MJT125_EMIF_SDREF_400MHz 0x00000C30
+#define MT41J128MJT125_ZQ_CFG_400MHz 0x50074BE4
+#define MT41J128MJT125_RATIO_400MHz 0x80
+#define MT41J128MJT125_INVERT_CLKOUT_400MHz 0x0
+#define MT41J128MJT125_RD_DQS_400MHz 0x3A
+#define MT41J128MJT125_WR_DQS_400MHz 0x3B
+#define MT41J128MJT125_PHY_WR_DATA_400MHz 0x76
+#define MT41J128MJT125_PHY_FIFO_WE_400MHz 0x96
+
+/* Micron MT41K128M16JT-187E */
+#define MT41K128MJT187E_EMIF_READ_LATENCY 0x06
+#define MT41K128MJT187E_EMIF_TIM1 0x0888B3DB
+#define MT41K128MJT187E_EMIF_TIM2 0x36337FDA
+#define MT41K128MJT187E_EMIF_TIM3 0x501F830F
+#define MT41K128MJT187E_EMIF_SDCFG 0x61C04AB2
+#define MT41K128MJT187E_EMIF_SDREF 0x0000093B
+#define MT41K128MJT187E_ZQ_CFG 0x50074BE4
+#define MT41K128MJT187E_RATIO 0x40
+#define MT41K128MJT187E_INVERT_CLKOUT 0x1
+#define MT41K128MJT187E_RD_DQS 0x3B
+#define MT41K128MJT187E_WR_DQS 0x85
+#define MT41K128MJT187E_PHY_WR_DATA 0xC1
+#define MT41K128MJT187E_PHY_FIFO_WE 0x100
+#define MT41K128MJT187E_IOCTRL_VALUE 0x18B
+
/* Micron MT41J64M16JT-125 */
#define MT41J64MJT125_EMIF_SDCFG 0x61C04A32
#define MT41J256MJT125_EMIF_SDCFG 0x61C04B32
/* Micron MT41J256M8HX-15E */
-#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x06
+#define MT41J256M8HX15E_EMIF_READ_LATENCY 0x100006
#define MT41J256M8HX15E_EMIF_TIM1 0x0888A39B
#define MT41J256M8HX15E_EMIF_TIM2 0x26337FDA
#define MT41J256M8HX15E_EMIF_TIM3 0x501F830F
#define MT41K256M16HA125E_IOCTRL_VALUE 0x18B
/* Micron MT41J512M8RH-125 on EVM v1.5 */
-#define MT41J512M8RH125_EMIF_READ_LATENCY 0x06
+#define MT41J512M8RH125_EMIF_READ_LATENCY 0x100006
#define MT41J512M8RH125_EMIF_TIM1 0x0888A39B
#define MT41J512M8RH125_EMIF_TIM2 0x26517FDA
#define MT41J512M8RH125_EMIF_TIM3 0x501F84EF
#define MT41J512M8RH125_IOCTRL_VALUE 0x18B
/* Samsung K4B2G1646E-BIH9 */
-#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x07
+#define K4B2G1646EBIH9_EMIF_READ_LATENCY 0x100007
#define K4B2G1646EBIH9_EMIF_TIM1 0x0AAAE51B
#define K4B2G1646EBIH9_EMIF_TIM2 0x2A1D7FDA
#define K4B2G1646EBIH9_EMIF_TIM3 0x501F83FF