am33xx: support board specific ddr settings

[oweals/u-boot.git] / arch / arm / include / asm / arch-am33xx / ddr_defs.h

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 7806e1b929a79a3a65c12ef00e8b24a1f1c797db..40a13e9d8dcaf6313747db2937bf97d0e703d105 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -26,11 +26,10 @@
 #define VTP_CTRL_READY         (0x1 << 5)
 #define VTP_CTRL_ENABLE                (0x1 << 6)
 #define VTP_CTRL_START_EN      (0x1)
-#define CMD_FORCE              0x00
-#define CMD_DELAY              0x00
 #define PHY_DLL_LOCK_DIFF      0x0
 #define DDR_CKE_CTRL_NORMAL    0x1
 
+/* Micron MT47H128M16RT-25E */
 #define DDR2_EMIF_READ_LATENCY 0x100005        /* Enable Dynamic Power Down */
 #define DDR2_EMIF_TIM1         0x0666B3C9
 #define DDR2_EMIF_TIM2         0x243631CA
@@ -49,6 +48,23 @@
 #define DDR2_PHY_RANK0_DELAY   0x1
 #define DDR2_IOCTRL_VALUE      0x18B
 
+/* Micron MT41J128M16JT-125 */
+#define DDR3_EMIF_READ_LATENCY 0x06
+#define DDR3_EMIF_TIM1         0x0888A39B
+#define DDR3_EMIF_TIM2         0x26337FDA
+#define DDR3_EMIF_TIM3         0x501F830F
+#define DDR3_EMIF_SDCFG                0x61C04AB2
+#define DDR3_EMIF_SDREF                0x0000093B
+#define DDR3_ZQ_CFG            0x50074BE4
+#define DDR3_DLL_LOCK_DIFF     0x1
+#define DDR3_RATIO             0x40
+#define DDR3_INVERT_CLKOUT     0x1
+#define DDR3_RD_DQS            0x3B
+#define DDR3_WR_DQS            0x85
+#define DDR3_PHY_WR_DATA       0xC1
+#define DDR3_PHY_FIFO_WE       0x100
+#define DDR3_IOCTRL_VALUE      0x18B
+
 /**
  * Configure SDRAM
  */
@@ -66,48 +82,43 @@ void config_ddr_phy(const struct emif_regs *regs);
 
 /**
  * This structure represents the DDR registers on AM33XX devices.
+ * We make use of DDR_PHY_BASE_ADDR2 to address the DATA1 registers that
+ * correspond to DATA1 registers defined here.
  */
 struct ddr_regs {
        unsigned int resv0[7];
        unsigned int cm0csratio;        /* offset 0x01C */
-       unsigned int cm0csforce;        /* offset 0x020 */
-       unsigned int cm0csdelay;        /* offset 0x024 */
+       unsigned int resv1[2];
        unsigned int cm0dldiff;         /* offset 0x028 */
        unsigned int cm0iclkout;        /* offset 0x02C */
-       unsigned int resv1[8];
+       unsigned int resv2[8];
        unsigned int cm1csratio;        /* offset 0x050 */
-       unsigned int cm1csforce;        /* offset 0x054 */
-       unsigned int cm1csdelay;        /* offset 0x058 */
+       unsigned int resv3[2];
        unsigned int cm1dldiff;         /* offset 0x05C */
        unsigned int cm1iclkout;        /* offset 0x060 */
-       unsigned int resv2[8];
+       unsigned int resv4[8];
        unsigned int cm2csratio;        /* offset 0x084 */
-       unsigned int cm2csforce;        /* offset 0x088 */
-       unsigned int cm2csdelay;        /* offset 0x08C */
+       unsigned int resv5[2];
        unsigned int cm2dldiff;         /* offset 0x090 */
        unsigned int cm2iclkout;        /* offset 0x094 */
-       unsigned int resv3[12];
+       unsigned int resv6[12];
        unsigned int dt0rdsratio0;      /* offset 0x0C8 */
-       unsigned int dt0rdsratio1;      /* offset 0x0CC */
-       unsigned int resv4[3];
+       unsigned int resv7[4];
        unsigned int dt0wdsratio0;      /* offset 0x0DC */
-       unsigned int dt0wdsratio1;      /* offset 0x0E0 */
-       unsigned int resv5[3];
+       unsigned int resv8[4];
        unsigned int dt0wiratio0;       /* offset 0x0F0 */
-       unsigned int dt0wiratio1;       /* offset 0x0F4 */
+       unsigned int resv9;
+       unsigned int dt0wimode0;        /* offset 0x0F8 */
        unsigned int dt0giratio0;       /* offset 0x0FC */
-       unsigned int dt0giratio1;       /* offset 0x100 */
-       unsigned int resv6[1];
+       unsigned int resv10;
+       unsigned int dt0gimode0;        /* offset 0x104 */
        unsigned int dt0fwsratio0;      /* offset 0x108 */
-       unsigned int dt0fwsratio1;      /* offset 0x10C */
-       unsigned int resv7[4];
+       unsigned int resv11[4];
+       unsigned int dt0dqoffset;       /* offset 0x11C */
        unsigned int dt0wrsratio0;      /* offset 0x120 */
-       unsigned int dt0wrsratio1;      /* offset 0x124 */
-       unsigned int resv8[3];
+       unsigned int resv12[4];
        unsigned int dt0rdelays0;       /* offset 0x134 */
        unsigned int dt0dldiff0;        /* offset 0x138 */
-       unsigned int resv9[39];
-       unsigned int dt1rdelays0;       /* offset 0x1D8 */
 };
 
 /**
@@ -136,17 +147,12 @@ struct cmd_control {
  */
 struct ddr_data {
        unsigned long datardsratio0;
-       unsigned long datardsratio1;
        unsigned long datawdsratio0;
-       unsigned long datawdsratio1;
        unsigned long datawiratio0;
-       unsigned long datawiratio1;
        unsigned long datagiratio0;
-       unsigned long datagiratio1;
        unsigned long datafwsratio0;
-       unsigned long datafwsratio1;
        unsigned long datawrsratio0;
-       unsigned long datawrsratio1;
+       unsigned long datauserank0delay;
        unsigned long datadldiff0;
 };
 
@@ -173,21 +179,10 @@ struct ddr_cmdtctrl {
        unsigned int dt1ioctl;
 };
 
-/**
- * Encapsulates DDR CMD & DATA io control registers.
- */
-struct ddr_ioctrl {
-       unsigned long cmd1ctl;
-       unsigned long cmd2ctl;
-       unsigned long cmd3ctl;
-       unsigned long data1ctl;
-       unsigned long data2ctl;
-};
-
 /**
  * Configure DDR io control registers
  */
-void config_io_ctrl(struct ddr_ioctrl *ioctrl);
+void config_io_ctrl(unsigned long val);
 
 struct ddr_ctrl {
        unsigned int ddrioctrl;
@@ -195,6 +190,8 @@ struct ddr_ctrl {
        unsigned int ddrckectrl;
 };
 
-void config_ddr(short ddr_type);
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+               const struct ddr_data *data, const struct cmd_control *ctrl,
+               const struct emif_regs *regs);
 
 #endif  /* _DDR_DEFS_H */