am33xx: support board specific ddr settings

[oweals/u-boot.git] / arch / arm / include / asm / arch-am33xx / ddr_defs.h

diff --git a/arch/arm/include/asm/arch-am33xx/ddr_defs.h b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
index 0526863693e1d2e08bbae0c6f2e2343ab89744f5..40a13e9d8dcaf6313747db2937bf97d0e703d105 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/ddr_defs.h
+++ b/arch/arm/include/asm/arch-am33xx/ddr_defs.h
@@ -29,6 +29,7 @@
 #define PHY_DLL_LOCK_DIFF      0x0
 #define DDR_CKE_CTRL_NORMAL    0x1
 
+/* Micron MT47H128M16RT-25E */
 #define DDR2_EMIF_READ_LATENCY 0x100005        /* Enable Dynamic Power Down */
 #define DDR2_EMIF_TIM1         0x0666B3C9
 #define DDR2_EMIF_TIM2         0x243631CA
@@ -47,6 +48,23 @@
 #define DDR2_PHY_RANK0_DELAY   0x1
 #define DDR2_IOCTRL_VALUE      0x18B
 
+/* Micron MT41J128M16JT-125 */
+#define DDR3_EMIF_READ_LATENCY 0x06
+#define DDR3_EMIF_TIM1         0x0888A39B
+#define DDR3_EMIF_TIM2         0x26337FDA
+#define DDR3_EMIF_TIM3         0x501F830F
+#define DDR3_EMIF_SDCFG                0x61C04AB2
+#define DDR3_EMIF_SDREF                0x0000093B
+#define DDR3_ZQ_CFG            0x50074BE4
+#define DDR3_DLL_LOCK_DIFF     0x1
+#define DDR3_RATIO             0x40
+#define DDR3_INVERT_CLKOUT     0x1
+#define DDR3_RD_DQS            0x3B
+#define DDR3_WR_DQS            0x85
+#define DDR3_PHY_WR_DATA       0xC1
+#define DDR3_PHY_FIFO_WE       0x100
+#define DDR3_IOCTRL_VALUE      0x18B
+
 /**
  * Configure SDRAM
  */
@@ -172,6 +190,8 @@ struct ddr_ctrl {
        unsigned int ddrckectrl;
 };
 
-void config_ddr(short ddr_type);
+void config_ddr(unsigned int pll, unsigned int ioctrl,
+               const struct ddr_data *data, const struct cmd_control *ctrl,
+               const struct emif_regs *regs);
 
 #endif  /* _DDR_DEFS_H */