Merge branch 'master' of git://git.denx.de/u-boot-ti

[oweals/u-boot.git] / arch / arm / include / asm / arch-am33xx / cpu.h

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index d9f0306b0abbff0a51611cb9d914bd809b4b992d..8dd69b3c80ee3022cb657720f217b3aaf8eb4568 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -26,7 +26,17 @@
 #define TCLR_PRE                       BIT(5)  /* Pre-scaler enable */
 #define TCLR_PTV_SHIFT                 (2)     /* Pre-scaler shift value */
 #define TCLR_PRE_DISABLE               CL_BIT(5) /* Pre-scalar disable */
-
+#define TCLR_CE                                BIT(6)  /* compare mode enable */
+#define TCLR_SCPWM                     BIT(7)  /* pwm outpin behaviour */
+#define TCLR_TCM                       BIT(8)  /* edge detection of input pin*/
+#define TCLR_TRG_SHIFT                 (10)    /* trigmode on pwm outpin */
+#define TCLR_PT                                BIT(12) /* pulse/toggle mode of outpin*/
+#define TCLR_CAPTMODE                  BIT(13) /* capture mode */
+#define TCLR_GPOCFG                    BIT(14) /* 0=output,1=input */
+
+#define TCFG_RESET                     BIT(0)  /* software reset */
+#define TCFG_EMUFREE                   BIT(1)  /* behaviour of tmr on debug */
+#define TCFG_IDLEMOD_SHIFT             (2)     /* power management */
 /* device type */
 #define DEVICE_MASK                    (BIT(8) | BIT(9) | BIT(10))
 #define TST_DEVICE                     0x0
@@ -87,7 +97,8 @@ struct cm_wkuppll {
        unsigned int wkctrlclkctrl;     /* offset 0x04 */
        unsigned int wkgpio0clkctrl;    /* offset 0x08 */
        unsigned int wkl4wkclkctrl;     /* offset 0x0c */
-       unsigned int resv2[4];
+       unsigned int timer0clkctrl;     /* offset 0x10 */
+       unsigned int resv2[3];
        unsigned int idlestdpllmpu;     /* offset 0x20 */
        unsigned int resv3[2];
        unsigned int clkseldpllmpu;     /* offset 0x2c */
@@ -121,7 +132,9 @@ struct cm_wkuppll {
        unsigned int wkup_uart0ctrl;    /* offset 0xB4 */
        unsigned int wkup_i2c0ctrl;     /* offset 0xB8 */
        unsigned int wkup_adctscctrl;   /* offset 0xBC */
-       unsigned int resv12[6];
+       unsigned int resv12;
+       unsigned int timer1clkctrl;     /* offset 0xC4 */
+       unsigned int resv13[4];
        unsigned int divm6dpllcore;     /* offset 0xD8 */
 };
 
@@ -178,7 +191,9 @@ struct cm_perpll {
        unsigned int epwmss2clkctrl;    /* offset 0xD8 */
        unsigned int l3instrclkctrl;    /* offset 0xDC */
        unsigned int l3clkctrl;         /* Offset 0xE0 */
-       unsigned int resv8[4];
+       unsigned int resv8[2];
+       unsigned int timer5clkctrl;     /* offset 0xEC */
+       unsigned int timer6clkctrl;     /* offset 0xF0 */
        unsigned int mmc1clkctrl;       /* offset 0xF4 */
        unsigned int mmc2clkctrl;       /* offset 0xF8 */
        unsigned int resv9[8];
@@ -191,9 +206,17 @@ struct cm_perpll {
 
 /* Encapsulating Display pll registers */
 struct cm_dpll {
-       unsigned int resv1[2];
+       unsigned int resv1;
+       unsigned int clktimer7clk;      /* offset 0x04 */
        unsigned int clktimer2clk;      /* offset 0x08 */
-       unsigned int resv2[10];
+       unsigned int clktimer3clk;      /* offset 0x0C */
+       unsigned int clktimer4clk;      /* offset 0x10 */
+       unsigned int resv2;
+       unsigned int clktimer5clk;      /* offset 0x18 */
+       unsigned int clktimer6clk;      /* offset 0x1C */
+       unsigned int resv3[2];
+       unsigned int clktimer1clk;      /* offset 0x28 */
+       unsigned int resv4[2];
        unsigned int clklcdcpixelclk;   /* offset 0x34 */
 };
 #else
@@ -466,6 +489,12 @@ struct ctrl_stat {
 #define OMAP_GPIO_SETDATAOUT           0x0194
 
 /* Control Device Register */
+
+ /* Control Device Register */
+#define MREQPRIO_0_SAB_INIT1_MASK      0xFFFFFF8F
+#define MREQPRIO_0_SAB_INIT0_MASK      0xFFFFFFF8
+#define MREQPRIO_1_DSS_MASK            0xFFFFFF8F
+
 struct ctrl_dev {
        unsigned int deviceid;          /* offset 0x00 */
        unsigned int resv1[7];
@@ -479,10 +508,25 @@ struct ctrl_dev {
        unsigned int macid1h;           /* offset 0x3c */
        unsigned int resv4[4];
        unsigned int miisel;            /* offset 0x50 */
-       unsigned int resv5[106];
+       unsigned int resv5[7];
+       unsigned int mreqprio_0;        /* offset 0x70 */
+       unsigned int mreqprio_1;        /* offset 0x74 */
+       unsigned int resv6[97];
        unsigned int efuse_sma;         /* offset 0x1FC */
 };
 
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+       u32 padding0[2];
+       u32 modena_init0_bw_fractional;
+       u32 modena_init0_bw_integer;
+       u32 modena_init0_watermark_0;
+};
+
 /* gmii_sel register defines */
 #define GMII1_SEL_MII          0x0
 #define GMII1_SEL_RMII         0x1