unsigned int clktimer2clk; /* offset 0x08 */
};
+/* Control Module RTC registers */
+struct cm_rtc {
+ unsigned int rtcclkctrl; /* offset 0x0 */
+ unsigned int clkstctrl; /* offset 0x4 */
+};
+
/* Watchdog timer registers */
struct wd_timer {
unsigned int resv1[4];
unsigned int tcar2; /* offset 0x58 */
};
+/* RTC Registers */
+struct rtc_regs {
+ unsigned int res[21];
+ unsigned int osc; /* offset 0x54 */
+ unsigned int res2[5];
+ unsigned int kick0r; /* offset 0x6c */
+ unsigned int kick1r; /* offset 0x70 */
+};
+
/* UART Registers */
struct uart_sys {
unsigned int resv1[21];
struct ctrl_stat {
unsigned int resv1[16];
unsigned int statusreg; /* ofset 0x40 */
+ unsigned int resv2[51];
+ unsigned int secure_emif_sdram_config; /* offset 0x0110 */
};
/* AM33XX GPIO registers */