Merge branch 'master' of git://git.denx.de/u-boot-mmc

[oweals/u-boot.git] / arch / arm / include / asm / arch-am33xx / cpu.h

diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h
index aa10fab4dd8be99b936eaaf90066340ce98ac0db..13a9cad23884ec409d95338d3ce3320d7a72154d 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/cpu.h
+++ b/arch/arm/include/asm/arch-am33xx/cpu.h
@@ -219,12 +219,22 @@ struct cm_dpll {
        unsigned int resv4[2];
        unsigned int clklcdcpixelclk;   /* offset 0x34 */
 };
+
+struct prm_device_inst {
+       unsigned int prm_rstctrl;
+       unsigned int prm_rsttime;
+       unsigned int prm_rstst;
+};
 #else
 /* Encapsulating core pll registers */
 struct cm_wkuppll {
        unsigned int resv0[136];
        unsigned int wkl4wkclkctrl;     /* offset 0x220 */
-       unsigned int resv1[55];
+       unsigned int resv1[7];
+       unsigned int usbphy0clkctrl;    /* offset 0x240 */
+       unsigned int resv112;
+       unsigned int usbphy1clkctrl;    /* offset 0x248 */
+       unsigned int resv113[45];
        unsigned int wkclkstctrl;       /* offset 0x300 */
        unsigned int resv2[15];
        unsigned int wkup_i2c0ctrl;     /* offset 0x340 */
@@ -283,7 +293,7 @@ struct cm_perpll {
        unsigned int l3clkstctrl;       /* offset 0x00 */
        unsigned int resv0[7];
        unsigned int l3clkctrl;         /* Offset 0x20 */
-       unsigned int resv1[7];
+       unsigned int resv112[7];
        unsigned int l3instrclkctrl;    /* offset 0x40 */
        unsigned int resv2[3];
        unsigned int ocmcramclkctrl;    /* offset 0x50 */
@@ -310,7 +320,9 @@ struct cm_perpll {
        unsigned int qspiclkctrl;       /* offset 0x258 */
        unsigned int resv121;
        unsigned int usb0clkctrl;       /* offset 0x260 */
-       unsigned int resv13[103];
+       unsigned int resv122;
+       unsigned int usb1clkctrl;       /* offset 0x268 */
+       unsigned int resv13[101];
        unsigned int l4lsclkstctrl;     /* offset 0x400 */
        unsigned int resv14[7];
        unsigned int l4lsclkctrl;       /* offset 0x420 */
@@ -364,10 +376,14 @@ struct cm_perpll {
        unsigned int uart4clkctrl;      /* offset 0x598 */
        unsigned int resv35;
        unsigned int uart5clkctrl;      /* offset 0x5A0 */
-       unsigned int resv36[87];
+       unsigned int resv36[5];
+       unsigned int usbphyocp2scp0clkctrl;     /* offset 0x5B8 */
+       unsigned int resv361;
+       unsigned int usbphyocp2scp1clkctrl;     /* offset 0x5C0 */
+       unsigned int resv3611[79];
 
        unsigned int emifclkstctrl;     /* offset 0x700 */
-       unsigned int resv361[7];
+       unsigned int resv362[7];
        unsigned int emifclkctrl;       /* offset 0x720 */
        unsigned int resv37[3];
        unsigned int emiffwclkctrl;     /* offset 0x730 */
@@ -386,9 +402,16 @@ struct cm_device_inst {
        unsigned int cm_dll_ctrl;
 };
 
+struct prm_device_inst {
+       unsigned int prm_rstctrl;
+       unsigned int prm_rstst;
+};
+
 struct cm_dpll {
        unsigned int resv1;
        unsigned int clktimer2clk;      /* offset 0x04 */
+       unsigned int resv2[11];
+       unsigned int clkselmacclk;      /* offset 0x34 */ 
 };
 #endif /* CONFIG_AM43XX */
 
@@ -489,6 +512,12 @@ struct ctrl_stat {
 #define OMAP_GPIO_SETDATAOUT           0x0194
 
 /* Control Device Register */
+
+ /* Control Device Register */
+#define MREQPRIO_0_SAB_INIT1_MASK      0xFFFFFF8F
+#define MREQPRIO_0_SAB_INIT0_MASK      0xFFFFFFF8
+#define MREQPRIO_1_DSS_MASK            0xFFFFFF8F
+
 struct ctrl_dev {
        unsigned int deviceid;          /* offset 0x00 */
        unsigned int resv1[7];
@@ -502,10 +531,25 @@ struct ctrl_dev {
        unsigned int macid1h;           /* offset 0x3c */
        unsigned int resv4[4];
        unsigned int miisel;            /* offset 0x50 */
-       unsigned int resv5[106];
+       unsigned int resv5[7];
+       unsigned int mreqprio_0;        /* offset 0x70 */
+       unsigned int mreqprio_1;        /* offset 0x74 */
+       unsigned int resv6[97];
        unsigned int efuse_sma;         /* offset 0x1FC */
 };
 
+/* Bandwidth Limiter Portion of the L3Fast Configuration Register */
+#define BW_LIMITER_BW_FRAC_MASK         0xFFFFFFE0
+#define BW_LIMITER_BW_INT_MASK          0xFFFFFFF0
+#define BW_LIMITER_BW_WATERMARK_MASK    0xFFFFF800
+
+struct l3f_cfg_bwlimiter {
+       u32 padding0[2];
+       u32 modena_init0_bw_fractional;
+       u32 modena_init0_bw_integer;
+       u32 modena_init0_watermark_0;
+};
+
 /* gmii_sel register defines */
 #define GMII1_SEL_MII          0x0
 #define GMII1_SEL_RMII         0x1