am33xx: support board specific ddr settings

[oweals/u-boot.git] / arch / arm / include / asm / arch-am33xx / clocks_am33xx.h

diff --git a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
index abc5b6b411dd47187049440ca9a6688199795780..d748dd27873a0bac3e75c00c63f8471fcd2c2108 100644 (file)
--- a/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
+++ b/arch/arm/include/asm/arch-am33xx/clocks_am33xx.h
@@ -19,16 +19,16 @@
 #ifndef _CLOCKS_AM33XX_H_
 #define _CLOCKS_AM33XX_H_
 
-#define OSC    24
+#define OSC    (V_OSCK/1000000)
 
 /* MAIN PLL Fdll = 550 MHZ, */
 #define MPUPLL_M       550
-#define MPUPLL_N       23
+#define MPUPLL_N       (OSC-1)
 #define MPUPLL_M2      1
 
 /* Core PLL Fdll = 1 GHZ, */
 #define COREPLL_M      1000
-#define COREPLL_N      23
+#define COREPLL_N      (OSC-1)
 
 #define COREPLL_M4     10      /* CORE_CLKOUTM4 = 200 MHZ */
 #define COREPLL_M5     8       /* CORE_CLKOUTM5 = 250 MHZ */
@@ -40,13 +40,13 @@
  * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
  */
 #define PERPLL_M       960
-#define PERPLL_N       23
+#define PERPLL_N       (OSC-1)
 #define PERPLL_M2      5
 
 /* DDR Freq is 266 MHZ for now */
 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
 #define DDRPLL_M       266
-#define DDRPLL_N       23
+#define DDRPLL_N       (OSC-1)
 #define DDRPLL_M2      1
 
 extern void pll_init(void);