armv7: add reset timeout to identify_nand_chip

[oweals/u-boot.git] / arch / arm / imx-common / init.c

diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c
index f1d43142a24c75af0af08f48cc9a2da9dbf0f345..3d2ce3a82e9addbd7a2ce735694b6a0b07b50d1c 100644 (file)
--- a/arch/arm/imx-common/init.c
+++ b/arch/arm/imx-common/init.c
@@ -44,8 +44,7 @@ void init_aips(void)
        writel(0x00000000, &aips2->opacr3);
        writel(0x00000000, &aips2->opacr4);
 
-       if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
-       {
+       if (is_mx6sx() || is_mx7()) {
                /*
                 * Set all MPROTx to be non-bufferable, trusted for R/W,
                 * not forced to user-mode.
@@ -66,6 +65,26 @@ void init_aips(void)
        }
 }
 
+void imx_set_wdog_powerdown(bool enable)
+{
+       struct wdog_regs *wdog1 = (struct wdog_regs *)WDOG1_BASE_ADDR;
+       struct wdog_regs *wdog2 = (struct wdog_regs *)WDOG2_BASE_ADDR;
+       struct wdog_regs *wdog3 = (struct wdog_regs *)WDOG3_BASE_ADDR;
+#ifdef CONFIG_MX7D
+       struct wdog_regs *wdog4 = (struct wdog_regs *)WDOG4_BASE_ADDR;
+#endif
+
+       /* Write to the PDE (Power Down Enable) bit */
+       writew(enable, &wdog1->wmcr);
+       writew(enable, &wdog2->wmcr);
+
+       if (is_mx6sx() || is_mx6ul() || is_mx7())
+               writew(enable, &wdog3->wmcr);
+#ifdef CONFIG_MX7D
+       writew(enable, &wdog4->wmcr);
+#endif
+}
+
 #define SRC_SCR_WARM_RESET_ENABLE      0
 
 void init_src(void)
@@ -82,6 +101,7 @@ void init_src(void)
        writel(val, &src_regs->scr);
 }
 
+#ifdef CONFIG_CMD_BMODE
 void boot_mode_apply(unsigned cfg_val)
 {
        unsigned reg;
@@ -94,3 +114,4 @@ void boot_mode_apply(unsigned cfg_val)
                reg &= ~(1 << 28);
        writel(reg, &psrc->gpr10);
 }
+#endif