#include <bootm.h>
#include <common.h>
#include <netdev.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
#include <asm/io.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/crm_regs.h>
+#include <imx_thermal.h>
#include <ipu_pixfmt.h>
#include <thermal.h>
#include <sata.h>
#include <fsl_esdhc.h>
#endif
-char *get_reset_cause(void)
+#if defined(CONFIG_DISPLAY_CPUINFO)
+static u32 reset_cause = -1;
+
+static char *get_reset_cause(void)
{
u32 cause;
struct src *src_regs = (struct src *)SRC_BASE_ADDR;
cause = readl(&src_regs->srsr);
writel(cause, &src_regs->srsr);
+ reset_cause = cause;
switch (cause) {
case 0x00001:
case 0x00008:
return "IPP USER";
case 0x00010:
+#ifdef CONFIG_MX7
+ return "WDOG1";
+#else
return "WDOG";
+#endif
case 0x00020:
return "JTAG HIGH-Z";
case 0x00040:
return "JTAG SW";
+ case 0x00080:
+ return "WDOG3";
+#ifdef CONFIG_MX7
+ case 0x00100:
+ return "WDOG4";
+ case 0x00200:
+ return "TEMPSENSE";
+#else
+ case 0x00100:
+ return "TEMPSENSE";
case 0x10000:
return "WARM BOOT";
+#endif
default:
return "unknown reset";
}
}
+u32 get_imx_reset_cause(void)
+{
+ return reset_cause;
+}
+#endif
+
#if defined(CONFIG_MX53) || defined(CONFIG_MX6)
#if defined(CONFIG_MX53)
#define MEMCTL_BASE ESDCTL_BASE_ADDR
const char *get_imx_type(u32 imxtype)
{
switch (imxtype) {
+ case MXC_CPU_MX7S:
+ return "7S"; /* Single-core version of the mx7 */
+ case MXC_CPU_MX7D:
+ return "7D"; /* Dual-core version of the mx7 */
+ case MXC_CPU_MX6QP:
+ return "6QP"; /* Quad-Plus version of the mx6 */
+ case MXC_CPU_MX6DP:
+ return "6DP"; /* Dual-Plus version of the mx6 */
case MXC_CPU_MX6Q:
return "6Q"; /* Quad-core version of the mx6 */
case MXC_CPU_MX6D:
return "6SOLO"; /* Solo version of the mx6 */
case MXC_CPU_MX6SL:
return "6SL"; /* Solo-Lite version of the mx6 */
+ case MXC_CPU_MX6SLL:
+ return "6SLL"; /* SLL version of the mx6 */
case MXC_CPU_MX6SX:
return "6SX"; /* SoloX version of the mx6 */
+ case MXC_CPU_MX6UL:
+ return "6UL"; /* Ultra-Lite version of the mx6 */
+ case MXC_CPU_MX6ULL:
+ return "6ULL"; /* ULL version of the mx6 */
case MXC_CPU_MX51:
return "51";
case MXC_CPU_MX53:
int print_cpuinfo(void)
{
u32 cpurev;
-
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
- struct udevice *thermal_dev;
- int cpu_tmp, ret;
-#endif
+ __maybe_unused u32 max_freq;
cpurev = get_cpu_rev();
+#if defined(CONFIG_IMX_THERMAL)
+ struct udevice *thermal_dev;
+ int cpu_tmp, minc, maxc, ret;
+
+ printf("CPU: Freescale i.MX%s rev%d.%d",
+ get_imx_type((cpurev & 0xFF000) >> 12),
+ (cpurev & 0x000F0) >> 4,
+ (cpurev & 0x0000F) >> 0);
+ max_freq = get_cpu_speed_grade_hz();
+ if (!max_freq || max_freq == mxc_get_clock(MXC_ARM_CLK)) {
+ printf(" at %dMHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ } else {
+ printf(" %d MHz (running at %d MHz)\n", max_freq / 1000000,
+ mxc_get_clock(MXC_ARM_CLK) / 1000000);
+ }
+#else
printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
get_imx_type((cpurev & 0xFF000) >> 12),
(cpurev & 0x000F0) >> 4,
(cpurev & 0x0000F) >> 0,
mxc_get_clock(MXC_ARM_CLK) / 1000000);
+#endif
-#if defined(CONFIG_MX6) && defined(CONFIG_IMX6_THERMAL)
+#if defined(CONFIG_IMX_THERMAL)
+ puts("CPU: ");
+ switch (get_cpu_temp_grade(&minc, &maxc)) {
+ case TEMP_AUTOMOTIVE:
+ puts("Automotive temperature grade ");
+ break;
+ case TEMP_INDUSTRIAL:
+ puts("Industrial temperature grade ");
+ break;
+ case TEMP_EXTCOMMERCIAL:
+ puts("Extended Commercial temperature grade ");
+ break;
+ default:
+ puts("Commercial temperature grade ");
+ break;
+ }
+ printf("(%dC to %dC)", minc, maxc);
ret = uclass_get_device(UCLASS_THERMAL, 0, &thermal_dev);
if (!ret) {
ret = thermal_get_temp(thermal_dev, &cpu_tmp);
if (!ret)
- printf("CPU: Temperature %d C\n", cpu_tmp);
+ printf(" at %dC\n", cpu_tmp);
else
- printf("CPU: Temperature: invalid sensor data\n");
+ debug(" - invalid sensor data\n");
} else {
- printf("CPU: Temperature: Can't find sensor device\n");
+ debug(" - invalid sensor device\n");
}
#endif
}
#endif
+#ifndef CONFIG_MX7
u32 get_ahb_clk(void)
{
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
return get_periph_clk() / (ahb_podf + 1);
}
+#endif
void arch_preboot_os(void)
{
/* disable video before launching O/S */
ipuv3_fb_shutdown();
#endif
+#if defined(CONFIG_VIDEO_MXS)
+ lcdif_power_down();
+#endif
}
void set_chipselect_size(int const cs_size)