/*
* dts file for Xilinx ZynqMP ZCU106
*
- * (C) Copyright 2016, Xilinx, Inc.
+ * (C) Copyright 2016 - 2020, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
*/
chosen {
bootargs = "earlycon";
stdout-path = "serial0:115200n8";
+ xlnx,eeprom = &eeprom;
};
memory@0 {
label = "sw19";
gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
linux,code = <KEY_DOWN>;
- gpio-key,wakeup;
+ wakeup-source;
autorepeat;
};
};
leds {
compatible = "gpio-leds";
- heartbeat_led {
+ heartbeat-led {
label = "heartbeat";
gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
linux,default-trigger = "heartbeat";
};
};
+
+ ina226-u76 {
+ compatible = "iio-hwmon";
+ io-channels = <&u76 0>, <&u76 1>, <&u76 2>, <&u76 3>;
+ };
+ ina226-u77 {
+ compatible = "iio-hwmon";
+ io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
+ };
+ ina226-u78 {
+ compatible = "iio-hwmon";
+ io-channels = <&u78 0>, <&u78 1>, <&u78 2>, <&u78 3>;
+ };
+ ina226-u87 {
+ compatible = "iio-hwmon";
+ io-channels = <&u87 0>, <&u87 1>, <&u87 2>, <&u87 3>;
+ };
+ ina226-u85 {
+ compatible = "iio-hwmon";
+ io-channels = <&u85 0>, <&u85 1>, <&u85 2>, <&u85 3>;
+ };
+ ina226-u86 {
+ compatible = "iio-hwmon";
+ io-channels = <&u86 0>, <&u86 1>, <&u86 2>, <&u86 3>;
+ };
+ ina226-u93 {
+ compatible = "iio-hwmon";
+ io-channels = <&u93 0>, <&u93 1>, <&u93 2>, <&u93 3>;
+ };
+ ina226-u88 {
+ compatible = "iio-hwmon";
+ io-channels = <&u88 0>, <&u88 1>, <&u88 2>, <&u88 3>;
+ };
+ ina226-u15 {
+ compatible = "iio-hwmon";
+ io-channels = <&u15 0>, <&u15 1>, <&u15 2>, <&u15 3>;
+ };
+ ina226-u92 {
+ compatible = "iio-hwmon";
+ io-channels = <&u92 0>, <&u92 1>, <&u92 2>, <&u92 3>;
+ };
+ ina226-u79 {
+ compatible = "iio-hwmon";
+ io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
+ };
+ ina226-u81 {
+ compatible = "iio-hwmon";
+ io-channels = <&u81 0>, <&u81 1>, <&u81 2>, <&u81 3>;
+ };
+ ina226-u80 {
+ compatible = "iio-hwmon";
+ io-channels = <&u80 0>, <&u80 1>, <&u80 2>, <&u80 3>;
+ };
+ ina226-u84 {
+ compatible = "iio-hwmon";
+ io-channels = <&u84 0>, <&u84 1>, <&u84 2>, <&u84 3>;
+ };
+ ina226-u16 {
+ compatible = "iio-hwmon";
+ io-channels = <&u16 0>, <&u16 1>, <&u16 2>, <&u16 3>;
+ };
+ ina226-u65 {
+ compatible = "iio-hwmon";
+ io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
+ };
+ ina226-u74 {
+ compatible = "iio-hwmon";
+ io-channels = <&u74 0>, <&u74 1>, <&u74 2>, <&u74 3>;
+ };
+ ina226-u75 {
+ compatible = "iio-hwmon";
+ io-channels = <&u75 0>, <&u75 1>, <&u75 2>, <&u75 3>;
+ };
};
&can1 {
status = "okay";
phy-handle = <&phy0>;
phy-mode = "rgmii-id";
- phy0: phy@c {
+ phy0: ethernet-phy@c {
reg = <0xc>;
ti,rx-internal-delay = <0x8>;
ti,tx-internal-delay = <0xa>;
ti,fifo-depth = <0x1>;
+ ti,dp83867-rxctrl-strap-quirk;
};
};
#size-cells = <0>;
reg = <0>;
/* PS_PMBUS */
- ina226@40 { /* u76 */
+ u76: ina226@40 { /* u76 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u76";
reg = <0x40>;
shunt-resistor = <5000>;
};
- ina226@41 { /* u77 */
+ u77: ina226@41 { /* u77 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u77";
reg = <0x41>;
shunt-resistor = <5000>;
};
- ina226@42 { /* u78 */
+ u78: ina226@42 { /* u78 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u78";
reg = <0x42>;
shunt-resistor = <5000>;
};
- ina226@43 { /* u87 */
+ u87: ina226@43 { /* u87 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u87";
reg = <0x43>;
shunt-resistor = <5000>;
};
- ina226@44 { /* u85 */
+ u85: ina226@44 { /* u85 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u85";
reg = <0x44>;
shunt-resistor = <5000>;
};
- ina226@45 { /* u86 */
+ u86: ina226@45 { /* u86 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u86";
reg = <0x45>;
shunt-resistor = <5000>;
};
- ina226@46 { /* u93 */
+ u93: ina226@46 { /* u93 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u93";
reg = <0x46>;
shunt-resistor = <5000>;
};
- ina226@47 { /* u88 */
+ u88: ina226@47 { /* u88 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u88";
reg = <0x47>;
shunt-resistor = <5000>;
};
- ina226@4a { /* u15 */
+ u15: ina226@4a { /* u15 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u15";
reg = <0x4a>;
shunt-resistor = <5000>;
};
- ina226@4b { /* u92 */
+ u92: ina226@4b { /* u92 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u92";
reg = <0x4b>;
shunt-resistor = <5000>;
};
#size-cells = <0>;
reg = <1>;
/* PL_PMBUS */
- ina226@40 { /* u79 */
+ u79: ina226@40 { /* u79 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u79";
reg = <0x40>;
shunt-resistor = <2000>;
};
- ina226@41 { /* u81 */
+ u81: ina226@41 { /* u81 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u81";
reg = <0x41>;
shunt-resistor = <5000>;
};
- ina226@42 { /* u80 */
+ u80: ina226@42 { /* u80 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u80";
reg = <0x42>;
shunt-resistor = <5000>;
};
- ina226@43 { /* u84 */
+ u84: ina226@43 { /* u84 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u84";
reg = <0x43>;
shunt-resistor = <5000>;
};
- ina226@44 { /* u16 */
+ u16: ina226@44 { /* u16 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u16";
reg = <0x44>;
shunt-resistor = <5000>;
};
- ina226@45 { /* u65 */
+ u65: ina226@45 { /* u65 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u65";
reg = <0x45>;
shunt-resistor = <5000>;
};
- ina226@46 { /* u74 */
+ u74: ina226@46 { /* u74 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u74";
reg = <0x46>;
shunt-resistor = <5000>;
};
- ina226@47 { /* u75 */
+ u75: ina226@47 { /* u75 */
compatible = "ti,ina226";
+ #io-channel-cells = <1>;
+ label = "ina226-u75";
reg = <0x47>;
shunt-resistor = <5000>;
};
#size-cells = <0>;
reg = <3>;
/* DDR4 SODIMM */
- dev@19 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x19>;
- };
- dev@30 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x30>;
- };
- dev@35 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x35>;
- };
- dev@36 { /* u-boot detection */
- compatible = "xxx";
- reg = <0x36>;
- };
- dev@51 { /* u-boot detection - maybe SPD */
- compatible = "xxx";
- reg = <0x51>;
- };
};
i2c@4 {
#address-cells = <1>;
status = "okay";
is-dual = <1>;
flash@0 {
- compatible = "m25p80", "spi-flash"; /* 32MB */
+ compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
#address-cells = <1>;
#size-cells = <1>;
reg = <0x0>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@qspi-fsbl-uboot { /* for testing purpose */
+ partition@0 { /* for testing purpose */
label = "qspi-fsbl-uboot";
reg = <0x0 0x100000>;
};
- partition@qspi-linux { /* for testing purpose */
+ partition@100000 { /* for testing purpose */
label = "qspi-linux";
reg = <0x100000 0x500000>;
};
- partition@qspi-device-tree { /* for testing purpose */
+ partition@600000 { /* for testing purpose */
label = "qspi-device-tree";
reg = <0x600000 0x20000>;
};
- partition@qspi-rootfs { /* for testing purpose */
+ partition@620000 { /* for testing purpose */
label = "qspi-rootfs";
reg = <0x620000 0x5E0000>;
};
/* SD1 with level shifter */
&sdhci1 {
status = "okay";
+ /*
+ * This property should be removed for supporting UHS mode
+ */
no-1-8-v;
xlnx,mio_bank = <1>;
};
projects / oweals / u-boot.git / blobdiff