ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / dts / zynqmp-zcu102-revB.dts

diff --git a/arch/arm/dts/zynqmp-zcu102-revB.dts b/arch/arm/dts/zynqmp-zcu102-revB.dts
index 765108e4378965c4f0c4cdc82f03fd2a5c27b630..2422558b7484ba12c6b844aad779800bee93d19d 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu102-revB.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revB.dts
@@ -1,39 +1,39 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevB
  *
- * (C) Copyright 2016, Xilinx, Inc.
+ * (C) Copyright 2016 - 2020, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
-#include "zynqmp-zcu102.dts"
+#include "zynqmp-zcu102-revA.dts"
 
 / {
        model = "ZynqMP ZCU102 RevB";
+       compatible = "xlnx,zynqmp-zcu102-revB", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
 };
 
 &gem3 {
        phy-handle = <&phyc>;
-       phyc: phy@c {
+       phyc: ethernet-phy@c {
                reg = <0xc>;
                ti,rx-internal-delay = <0x8>;
                ti,tx-internal-delay = <0xa>;
                ti,fifo-depth = <0x1>;
+               ti,dp83867-rxctrl-strap-quirk;
+               /* reset-gpios = <&tca6416_u97 6 GPIO_ACTIVE_LOW>; */
        };
        /* Cleanup from RevA */
-       /delete-node/ phy@21;
+       /delete-node/ ethernet-phy@21;
 };
 
-/* Different qspi 512Mbit version */
-
 /* Fix collision with u61 */
 &i2c0 {
-       i2cswitch@75 {
+       i2c-mux@75 {
                i2c@2 {
                        max15303@1b { /* u8 */
-                               compatible = "max15303";
+                               compatible = "maxim,max15303";
                                reg = <0x1b>;
                        };
                        /delete-node/ max15303@20;