rockchip: rk3328: rock64 - fix gen3 SPL hang

[oweals/u-boot.git] / arch / arm / dts / zynqmp-zcu102-revA.dts

diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts
index 78110c490e8d5bdba8719115e331a594bd5729ff..d250681600a85cc1a29b9a980308f8a541e22c20 100644 (file)
--- a/arch/arm/dts/zynqmp-zcu102-revA.dts
+++ b/arch/arm/dts/zynqmp-zcu102-revA.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP ZCU102 RevA
  *
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2020, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
@@ -51,14 +51,14 @@
                        label = "sw19";
                        gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
                        linux,code = <KEY_DOWN>;
-                       gpio-key,wakeup;
+                       wakeup-source;
                        autorepeat;
                };
        };
 
        leds {
                compatible = "gpio-leds";
-               heartbeat_led {
+               heartbeat-led {
                        label = "heartbeat";
                        gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
                        linux,default-trigger = "heartbeat";
@@ -213,25 +213,25 @@
                gpio-line-names = "PS_GTR_LAN_SEL0", "PS_GTR_LAN_SEL1", "PS_GTR_LAN_SEL2", "PS_GTR_LAN_SEL3",
                                "PCI_CLK_DIR_SEL", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B",
                                "", "", "", "", "", "", "", "", "";
-               gtr_sel0 {
+               gtr-sel0 {
                        gpio-hog;
                        gpios = <0 0>;
                        output-low; /* PCIE = 0, DP = 1 */
                        line-name = "sel0";
                };
-               gtr_sel1 {
+               gtr-sel1 {
                        gpio-hog;
                        gpios = <1 0>;
                        output-high; /* PCIE = 0, DP = 1 */
                        line-name = "sel1";
                };
-               gtr_sel2 {
+               gtr-sel2 {
                        gpio-hog;
                        gpios = <2 0>;
                        output-high; /* PCIE = 0, USB0 = 1 */
                        line-name = "sel2";
                };
-               gtr_sel3 {
+               gtr-sel3 {
                        gpio-hog;
                        gpios = <3 0>;
                        output-high; /* PCIE = 0, SATA = 1 */
@@ -614,19 +614,19 @@
                spi-tx-bus-width = <1>;
                spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
-               partition@qspi-fsbl-uboot { /* for testing purpose */
+               partition@0 { /* for testing purpose */
                        label = "qspi-fsbl-uboot";
                        reg = <0x0 0x100000>;
                };
-               partition@qspi-linux { /* for testing purpose */
+               partition@100000 { /* for testing purpose */
                        label = "qspi-linux";
                        reg = <0x100000 0x500000>;
                };
-               partition@qspi-device-tree { /* for testing purpose */
+               partition@600000 { /* for testing purpose */
                        label = "qspi-device-tree";
                        reg = <0x600000 0x20000>;
                };
-               partition@qspi-rootfs { /* for testing purpose */
+               partition@620000 { /* for testing purpose */
                        label = "qspi-rootfs";
                        reg = <0x620000 0x5E0000>;
                };
@@ -655,7 +655,11 @@
 /* SD1 with level shifter */
 &sdhci1 {
        status = "okay";
-       no-1-8-v;       /* for 1.0 silicon */
+       /*
+        * 1.0 revision has level shifter and this property should be
+        * removed for supporting UHS mode
+        */
+       no-1-8-v;
        xlnx,mio_bank = <1>;
 };
 
@@ -701,33 +705,23 @@
        status = "okay";
 };
 
-&xilinx_drm {
+&zynqmp_dpsub {
        status = "okay";
-       clocks = <&si570_1>;
 };
 
-&xlnx_dp {
+&zynqmp_dp_snd_codec0 {
        status = "okay";
 };
 
-&xlnx_dp_sub {
+&zynqmp_dp_snd_pcm0 {
        status = "okay";
-       xlnx,vid-clk-pl;
 };
 
-&xlnx_dp_snd_pcm0 {
+&zynqmp_dp_snd_pcm1 {
        status = "okay";
 };
 
-&xlnx_dp_snd_pcm1 {
-       status = "okay";
-};
-
-&xlnx_dp_snd_card {
-       status = "okay";
-};
-
-&xlnx_dp_snd_codec0 {
+&zynqmp_dp_snd_card0 {
        status = "okay";
 };