Merge branch 'master' of git://git.denx.de/u-boot-sh

[oweals/u-boot.git] / arch / arm / dts / zynqmp-zc1751-xm018-dc4.dts

diff --git a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
index 799b87a04c13ed11d6337eee34f8de1e36692ab0..84c2904dc202a59e2fcdb47f367140fa3657e156 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm018-dc4.dts
@@ -1,17 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * dts file for Xilinx ZynqMP zc1751-xm018-dc4
  *
- * (C) Copyright 2015 - 2016, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 /dts-v1/;
 
 #include "zynqmp.dtsi"
-#include "zynqmp-clk.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
 
 / {
        model = "ZynqMP zc1751-xm018-dc4";
@@ -52,19 +51,12 @@
        status = "okay";
 };
 
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
        status = "okay";
-       xlnx,include-sg; /* for testing purpose */
-       xlnx,overfetch; /* for testing purpose */
-       xlnx,ratectrl = <0>; /* for testing purpose */
-       xlnx,src-issue = <31>;
 };
 
 &fpd_dma_chan2 {
        status = "okay";
-       xlnx,ratectrl = <100>; /* for testing purpose */
-       xlnx,src-issue = <4>; /* for testing purpose */
 };
 
 &fpd_dma_chan3 {
@@ -73,7 +65,6 @@
 
 &fpd_dma_chan4 {
        status = "okay";
-       xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan5 {
@@ -82,7 +73,6 @@
 
 &fpd_dma_chan6 {
        status = "okay";
-       xlnx,include-sg; /* for testing purpose */
 };
 
 &fpd_dma_chan7 {
@@ -91,7 +81,6 @@
 
 &fpd_dma_chan8 {
        status = "okay";
-       xlnx,include-sg; /* for testing purpose */
 };
 
 &lpd_dma_chan1 {
@@ -188,6 +177,35 @@
        status = "okay";
 };
 
+&qspi {
+       status = "okay";
+       flash@0 {
+               compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               reg = <0x0>;
+               spi-tx-bus-width = <1>;
+               spi-rx-bus-width = <4>; /* also DUAL configuration possible */
+               spi-max-frequency = <108000000>; /* Based on DC1 spec */
+               partition@qspi-fsbl-uboot { /* for testing purpose */
+                       label = "qspi-fsbl-uboot";
+                       reg = <0x0 0x100000>;
+               };
+               partition@qspi-linux { /* for testing purpose */
+                       label = "qspi-linux";
+                       reg = <0x100000 0x500000>;
+               };
+               partition@qspi-device-tree { /* for testing purpose */
+                       label = "qspi-device-tree";
+                       reg = <0x600000 0x20000>;
+               };
+               partition@qspi-rootfs { /* for testing purpose */
+                       label = "qspi-rootfs";
+                       reg = <0x620000 0x5E0000>;
+               };
+       };
+};
+
 &rtc {
        status = "okay";
 };