ARM: dts: sama5d2: Add uart4 definition

[oweals/u-boot.git] / arch / arm / dts / zynqmp-zc1751-xm015-dc1.dts

diff --git a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
index 0ddb43df6d4f7f3ce5e28edc1aa4fc183da9ba6f..0805b93c4ac953c511d0d40934b5ed0957afcc06 100644 (file)
--- a/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
+++ b/arch/arm/dts/zynqmp-zc1751-xm015-dc1.dts
@@ -2,7 +2,7 @@
 /*
  * dts file for Xilinx ZynqMP zc1751-xm015-dc1
  *
- * (C) Copyright 2015 - 2018, Xilinx, Inc.
+ * (C) Copyright 2015 - 2020, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
  */
@@ -39,7 +39,6 @@
        };
 };
 
-/* fpd_dma clk 667MHz, lpd_dma 500MHz */
 &fpd_dma_chan1 {
        status = "okay";
 };
@@ -76,7 +75,7 @@
        status = "okay";
        phy-handle = <&phy0>;
        phy-mode = "rgmii-id";
-       phy0: phy@0 {
+       phy0: ethernet-phy@0 {
                reg = <0>;
        };
 };
@@ -92,8 +91,9 @@
 &i2c1 {
        status = "okay";
        clock-frequency = <400000>;
-       eeprom@55 {
-               compatible = "at,24c64"; /* 24AA64 */
+
+       eeprom: eeprom@55 {
+               compatible = "atmel,24c64"; /* 24AA64 */
                reg = <0x55>;
        };
 };
@@ -101,26 +101,26 @@
 &qspi {
        status = "okay";
        flash@0 {
-               compatible = "m25p80"; /* Micron MT25QU512ABB8ESF */
+               compatible = "m25p80", "jedec,spi-nor"; /* Micron MT25QU512ABB8ESF */
                #address-cells = <1>;
                #size-cells = <1>;
                reg = <0x0>;
                spi-tx-bus-width = <1>;
                spi-rx-bus-width = <4>;
                spi-max-frequency = <108000000>; /* Based on DC1 spec */
-               partition@qspi-fsbl-uboot { /* for testing purpose */
+               partition@0 { /* for testing purpose */
                        label = "qspi-fsbl-uboot";
                        reg = <0x0 0x100000>;
                };
-               partition@qspi-linux { /* for testing purpose */
+               partition@100000 { /* for testing purpose */
                        label = "qspi-linux";
                        reg = <0x100000 0x500000>;
                };
-               partition@qspi-device-tree { /* for testing purpose */
+               partition@600000 { /* for testing purpose */
                        label = "qspi-device-tree";
                        reg = <0x600000 0x20000>;
                };
-               partition@qspi-rootfs { /* for testing purpose */
+               partition@620000 { /* for testing purpose */
                        label = "qspi-rootfs";
                        reg = <0x620000 0x5E0000>;
                };
@@ -154,7 +154,10 @@
 /* SD1 with level shifter */
 &sdhci1 {
        status = "okay";
-       no-1-8-v;       /* for 1.0 silicon */
+       /*
+        * This property should be removed for supporting UHS mode
+        */
+       no-1-8-v;
        xlnx,mio_bank = <1>;
 };
 
@@ -172,32 +175,23 @@
        dr_mode = "host";
 };
 
-&xilinx_drm {
-       status = "okay";
-};
-
-&xlnx_dp {
-       status = "okay";
-};
-
-&xlnx_dp_sub {
+&zynqmp_dpsub {
        status = "okay";
-       xlnx,vid-clk-pl;
 };
 
-&xlnx_dp_snd_pcm0 {
+&zynqmp_dp_snd_pcm0 {
        status = "okay";
 };
 
-&xlnx_dp_snd_pcm1 {
+&zynqmp_dp_snd_pcm1 {
        status = "okay";
 };
 
-&xlnx_dp_snd_card {
+&zynqmp_dp_snd_card0 {
        status = "okay";
 };
 
-&xlnx_dp_snd_codec0 {
+&zynqmp_dp_snd_codec0 {
        status = "okay";
 };