+// SPDX-License-Identifier: GPL-2.0+
/*
* Clock specification for Xilinx ZynqMP
*
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
*
* Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
-&amba {
+/ {
clk100: clk100 {
compatible = "fixed-clock";
#clock-cells = <0>;
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <200000000>;
+ u-boot,dm-pre-reloc;
};
clk250: clk250 {
};
&watchdog0 {
- clocks = <&clk250>;
+ clocks = <&clk100>;
};
&xilinx_drm {