Merge https://gitlab.denx.de/u-boot/custodians/u-boot-clk

[oweals/u-boot.git] / arch / arm / dts / zynqmp-clk.dtsi

diff --git a/arch/arm/dts/zynqmp-clk.dtsi b/arch/arm/dts/zynqmp-clk.dtsi
index 0918c686d70ea557a3bc7658b4fbae57388516ad..a795efdc15c8c5f4e77cf717714a0950d21b058b 100644 (file)
--- a/arch/arm/dts/zynqmp-clk.dtsi
+++ b/arch/arm/dts/zynqmp-clk.dtsi
@@ -1,14 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Clock specification for Xilinx ZynqMP
  *
- * (C) Copyright 2015, Xilinx, Inc.
+ * (C) Copyright 2015 - 2018, Xilinx, Inc.
  *
  * Michal Simek <michal.simek@xilinx.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
-&amba {
+/ {
        clk100: clk100 {
                compatible = "fixed-clock";
                #clock-cells = <0>;
@@ -26,6 +25,7 @@
                compatible = "fixed-clock";
                #clock-cells = <0>;
                clock-frequency = <200000000>;
+               u-boot,dm-pre-reloc;
        };
 
        clk250: clk250 {
@@ -114,6 +114,38 @@
        clocks = <&clk600>, <&clk100>;
 };
 
+&lpd_dma_chan1 {
+       clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan2 {
+       clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan3 {
+       clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan4 {
+       clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan5 {
+       clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan6 {
+       clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan7 {
+       clocks = <&clk600>, <&clk100>;
+};
+
+&lpd_dma_chan8 {
+       clocks = <&clk600>, <&clk100>;
+};
+
 &nand0 {
        clocks = <&clk100 &clk100>;
 };
@@ -186,6 +218,10 @@
        clocks = <&clk250>, <&clk250>;
 };
 
+&watchdog0 {
+       clocks = <&clk100>;
+};
+
 &xilinx_drm {
        clocks = <&drm_clock>;
 };