arm: dts: rockchip: px30: add and enable rng node

[oweals/u-boot.git] / arch / arm / dts / zynq-zed.dts

diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts
index 4363a4fcaccb10f61f986e86ac07ed0b663189cc..7a540b63f47135584710e0c7d0b51b8fde63cc5b 100644 (file)
--- a/arch/arm/dts/zynq-zed.dts
+++ b/arch/arm/dts/zynq-zed.dts
@@ -1,17 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * Xilinx ZED board DTS
- *
  *  Copyright (C) 2011 - 2015 Xilinx
  *  Copyright (C) 2012 National Instruments Corp.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 /dts-v1/;
 #include "zynq-7000.dtsi"
 
 / {
-       model = "Zynq Zed Development Board";
-       compatible = "xlnx,zynq-zed", "xlnx,zynq-7000";
+       model = "Avnet ZedBoard board";
+       compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000";
 
        aliases {
                ethernet0 = &gem0;
@@ -20,7 +17,7 @@
                mmc0 = &sdhci0;
        };
 
-       memory {
+       memory@0 {
                device_type = "memory";
                reg = <0x0 0x20000000>;
        };
@@ -47,12 +44,20 @@
 
        ethernet_phy: ethernet-phy@0 {
                reg = <0>;
+               device_type = "ethernet-phy";
        };
 };
 
 &qspi {
        u-boot,dm-pre-reloc;
        status = "okay";
+       num-cs = <1>;
+       flash@0 {
+               compatible = "spansion,s25fl256s", "jedec,spi-nor";
+               reg = <0>;
+               spi-max-frequency = <30000000>;
+               m25p,fast-read;
+       };
 };
 
 &sdhci0 {