+// SPDX-License-Identifier: GPL-2.0+
/*
* Xilinx ZC770 XM010 board DTS
*
- * Copyright (C) 2013 - 2015 Xilinx, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (C) 2013-2018 Xilinx, Inc.
*/
/dts-v1/;
#include "zynq-7000.dtsi"
/ {
+ model = "Xilinx ZC770 XM010 board";
compatible = "xlnx,zynq-zc770-xm010", "xlnx,zynq-7000";
- model = "Xilinx Zynq";
aliases {
ethernet0 = &gem0;
};
chosen {
- bootargs = "root=/dev/ram rw earlyprintk";
+ bootargs = "";
stdout-path = "serial0:115200n8";
};
- memory {
+ memory@0 {
device_type = "memory";
reg = <0x0 0x40000000>;
};
};
};
-&spi1 {
- status = "okay";
- num-cs = <4>;
- is-decoded-cs = <0>;
- flash@0 {
- compatible = "sst25wf080";
- reg = <1>;
- spi-max-frequency = <1000000>;
- #address-cells = <1>;
- #size-cells = <1>;
- partition@test {
- label = "spi-flash";
- reg = <0x0 0x100000>;
- };
- };
-};
-
-&qspi {
- status = "okay";
-};
-
&can0 {
status = "okay";
};
ethernet_phy: ethernet-phy@7 {
reg = <7>;
+ device_type = "ethernet-phy";
};
};
status = "okay";
clock-frequency = <400000>;
- m24c02_eeprom@52 {
- compatible = "at,24c02";
+ eeprom: eeprom@52 {
+ compatible = "atmel,24c02";
reg = <0x52>;
};
+};
+&qspi {
+ status = "okay";
};
&sdhci0 {
status = "okay";
};
+&spi1 {
+ status = "okay";
+ num-cs = <4>;
+ is-decoded-cs = <0>;
+ flash@1 {
+ compatible = "sst25wf080", "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <1000000>;
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "data";
+ reg = <0x0 0x100000>;
+ };
+ };
+ };
+};
+
&uart1 {
u-boot,dm-pre-reloc;
status = "okay";