Merge tag 'u-boot-imx-20191009' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

[oweals/u-boot.git] / arch / arm / dts / zynq-7000.dtsi

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi
index 0b62cb093658a79de876e015985a7b92e9135103..e1b0816a3459cb340784a07a1bb47aaf9f93e950 100644 (file)
--- a/arch/arm/dts/zynq-7000.dtsi
+++ b/arch/arm/dts/zynq-7000.dtsi
@@ -1,21 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Xilinx Zynq 7000 DTSI
  * Describes the hardware common to all Zynq 7000-based boards.
  *
  *  Copyright (C) 2011 - 2015 Xilinx
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
-/include/ "skeleton.dtsi"
 
 / {
+       #address-cells = <1>;
+       #size-cells = <1>;
        compatible = "xlnx,zynq-7000";
 
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
 
-               cpu@0 {
+               cpu0: cpu@0 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <0>;
@@ -29,7 +29,7 @@
                        >;
                };
 
-               cpu@1 {
+               cpu1: cpu@1 {
                        compatible = "arm,cortex-a9";
                        device_type = "cpu";
                        reg = <1>;
@@ -37,14 +37,23 @@
                };
        };
 
-       pmu {
+       fpga_full: fpga-full {
+               compatible = "fpga-region";
+               fpga-mgr = <&devcfg>;
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+       };
+
+       pmu@f8891000 {
                compatible = "arm,cortex-a9-pmu";
                interrupts = <0 5 4>, <0 6 4>;
                interrupt-parent = <&intc>;
-               reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
+               reg = <0xf8891000 0x1000>,
+                     <0xf8893000 0x1000>;
        };
 
-       regulator_vccpint: fixedregulator@0 {
+       regulator_vccpint: fixedregulator {
                compatible = "regulator-fixed";
                regulator-name = "VCCPINT";
                regulator-min-microvolt = <1000000>;
@@ -54,6 +63,7 @@
        };
 
        amba: amba {
+               u-boot,dm-pre-reloc;
                compatible = "simple-bus";
                #address-cells = <1>;
                #size-cells = <1>;
@@ -97,6 +107,8 @@
                        #gpio-cells = <2>;
                        clocks = <&clkc 42>;
                        gpio-controller;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
                        interrupt-parent = <&intc>;
                        interrupts = <0 20 4>;
                        reg = <0xe000a000 0x1000>;
@@ -173,7 +185,6 @@
                        interrupts = <0 26 4>;
                        clocks = <&clkc 25>, <&clkc 34>;
                        clock-names = "ref_clk", "pclk";
-                       spi-max-frequency = <166666700>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
@@ -186,7 +197,18 @@
                        interrupts = <0 49 4>;
                        clocks = <&clkc 26>, <&clkc 35>;
                        clock-names = "ref_clk", "pclk";
-                       spi-max-frequency = <166666700>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+
+               qspi: spi@e000d000 {
+                       clock-names = "ref_clk", "pclk";
+                       clocks = <&clkc 10>, <&clkc 43>;
+                       compatible = "xlnx,zynq-qspi-1.0";
+                       status = "disabled";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 19 4>;
+                       reg = <0xe000d000 0x1000>;
                        #address-cells = <1>;
                        #size-cells = <0>;
                };
@@ -213,7 +235,7 @@
                        #size-cells = <0>;
                };
 
-               sdhci0: sdhci@e0100000 {
+               sdhci0: mmc@e0100000 {
                        compatible = "arasan,sdhci-8.9a";
                        status = "disabled";
                        clock-names = "clk_xin", "clk_ahb";
@@ -221,9 +243,9 @@
                        interrupt-parent = <&intc>;
                        interrupts = <0 24 4>;
                        reg = <0xe0100000 0x1000>;
-               } ;
+               };
 
-               sdhci1: sdhci@e0101000 {
+               sdhci1: mmc@e0101000 {
                        compatible = "arasan,sdhci-8.9a";
                        status = "disabled";
                        clock-names = "clk_xin", "clk_ahb";
@@ -231,15 +253,17 @@
                        interrupt-parent = <&intc>;
                        interrupts = <0 47 4>;
                        reg = <0xe0101000 0x1000>;
-               } ;
+               };
 
                slcr: slcr@f8000000 {
+                       u-boot,dm-pre-reloc;
                        #address-cells = <1>;
                        #size-cells = <1>;
-                       compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
+                       compatible = "xlnx,zynq-slcr", "syscon", "simple-mfd";
                        reg = <0xF8000000 0x1000>;
                        ranges;
                        clkc: clkc@100 {
+                               u-boot,dm-pre-reloc;
                                #clock-cells = <1>;
                                compatible = "xlnx,ps7-clkc";
                                fclk-enable = <0>;
@@ -257,6 +281,13 @@
                                reg = <0x100 0x100>;
                        };
 
+                       rstc: rstc@200 {
+                               compatible = "xlnx,zynq-reset";
+                               reg = <0x200 0x48>;
+                               #reset-cells = <1>;
+                               syscon = <&slcr>;
+                       };
+
                        pinctrl0: pinctrl@700 {
                                compatible = "xlnx,pinctrl-zynq";
                                reg = <0x700 0x200>;
@@ -284,7 +315,17 @@
 
                devcfg: devcfg@f8007000 {
                        compatible = "xlnx,zynq-devcfg-1.0";
+                       interrupt-parent = <&intc>;
+                       interrupts = <0 8 4>;
                        reg = <0xf8007000 0x100>;
+                       clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
+                       clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
+                       syscon = <&slcr>;
+               };
+
+               efuse: efuse@f800d000 {
+                       compatible = "xlnx,zynq-efuse";
+                       reg = <0xf800d000 0x20>;
                };
 
                global_timer: timer@f8f00200 {
@@ -313,11 +354,11 @@
 
                scutimer: timer@f8f00600 {
                        interrupt-parent = <&intc>;
-                       interrupts = < 1 13 0x301 >;
+                       interrupts = <1 13 0x301>;
                        compatible = "arm,cortex-a9-twd-timer";
-                       reg = < 0xf8f00600 0x20 >;
+                       reg = <0xf8f00600 0x20>;
                        clocks = <&clkc 4>;
-               } ;
+               };
 
                usb0: usb@e0002000 {
                        compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";